00:38 <rjo> lekernel: sorry. that patch was supposed to have max(2, n)

00:38 <rjo> lekernel: i got my ones and twos wrong....

07:36 <GitHub86> [migen] sbourdeauducq pushed 1 new commit to master: http://git.io/sR-elQ

07:36 <GitHub86> migen/master 6e11954 Robert Jordens: genlib/roundrobin: fix n==1 case (correctly)

09:25 <ysionneau> lekernel: about my email in moderation, do you want me to send it again with no attached files and with links instead? (the whole email was 200 kB instead of the 40 kB which is the max accepted)

09:26 <cde> shouldn't we increase that limit a bit

09:32 <lekernel> just moderated it

09:50 <ysionneau> thanks :)

09:50 <ysionneau> cde: 40 kB is a bit low indeed at least for PDF files :)

09:52 <cde> maybe it's a good thing. PDF is evil ;)

09:53 <cde> let's share .tex or .rst

09:53 <cde> btw https://code.google.com/p/wavedrom/ <= very nice for sharing waveforms

09:54 <ysionneau> cool :)

10:44 <stekern> ysionneau: that was a nice and comprehensible documentation of the mmu, there's only one thing that I'm not sure about - the value written to TLBBADVADDR on an itlb miss

10:45 <stekern> in the document it sounds like it's not updated with the address that actually caused the miss, but whatever happens to be in execute stage

10:45 <stekern> is that right?

11:58 <GitHub168> [migen] sbourdeauducq pushed 1 new commit to master: http://git.io/H5mP8g

11:58 <GitHub168> migen/master cec8fc4 Sebastien Bourdeauducq: fhdl/specials/Instance: fix item sorting

11:58 <ysionneau> 12:44 < stekern> ysionneau: that was a nice and comprehensible documentation of the mmu < thanks :)

12:00 <ysionneau> hum reading the paragraph again I'm not sure it's correct

12:24 <ysionneau> stekern: I will look closer at this paragraph tonight I think :)

12:24 <ysionneau> thanks for the feedback!

12:59 <stekern> ysionneau: my pleasure

12:59 <ysionneau> I think mwalle already told me about this paragraph, I thought I had address this issue

12:59 <ysionneau> it seems not

13:16 <GitHub161> [mibuild] sbourdeauducq pushed 1 new commit to master: http://git.io/yM_miA

13:16 <GitHub161> mibuild/master f7f19b7 Sebastien Bourdeauducq: Fragment -> _Fragment

13:26 <stekern> I know how it is. When you looked too long at your own documentation, errors start becoming hard to find =P

13:27 <stekern> I'm curious though, how does the exceptions work in lm32. I guess for exceptions that happen in < execute stage, they are just propagated into execute and then taken

13:29 <stekern> but are all mem stage (apart from mmu) exceptions just address related?

13:30 <stekern> (i.e. any external bus errors can't be captured?)

13:31 <ysionneau> 15:27 < stekern> I'm curious though, how does the exceptions work in lm32. I guess for exceptions that happen in < execute stage, they are just propagated into execute and then taken < yes, when the exception is raised, it is really triggered once the instruction is in the X stage

13:31 <ysionneau> documentation says that bus error exception are more or less non deterministic :)

13:32 <ysionneau> I think that there is no easy way to raise an exception after the execute stage in the lm32 pipeline

13:32 <stekern> ok, yes, that makes sense

13:32 <stekern> and I think I recall that you had to induce a 1 cycle delay for the dtlb miss exception just because of this, right?

13:32 <ysionneau> indeed

13:33 <ysionneau> so that the instruction (load or store) is still in the X stage

13:39 <ysionneau> stekern: after checking in the code, the sentence in the documentation is correct

13:39 <ysionneau> cf https://github.com/milkymist/lm32/blob/master/rtl/lm32_cpu.v#L2501

13:39 <stekern> I wonder though, does execute stage have any sideeffects that wouldn't be cleared by the dtlb miss exceptions? (if it would be taken in mem stage I mean)

13:40 <stekern> (as a comparison, in mor1kx we take all exceptions in mem stage)

13:42 <stekern> hmm, yes, but hasn't the itlb miss pc moved up to execute stage when that happens?

13:43 <stekern> or is the 'itlb_exception' signal connected straight from the mmu?

13:45 <ysionneau> it's connected straight from the mmu

13:45 <GitHub164> [migen] sbourdeauducq pushed 1 new commit to master: http://git.io/3bP_Ug

13:45 <GitHub164> migen/master 9c7ad6b Sebastien Bourdeauducq: fhdl: RenameClockDomains decorator

13:45 <GitHub56> [milkymist-ng] sbourdeauducq pushed 1 new commit to master: http://git.io/eHExVQ

13:45 <GitHub56> milkymist-ng/master bf32559 Sebastien Bourdeauducq: Use RenameClockDomains decorator instead of add_submodule

13:46 <ysionneau> oh you're right

13:47 <ysionneau> itlb_miss_x comes from the itlb module but it's "buffered" from the miss_f

13:47 <ysionneau> miss_x <= miss_d; and miss_d <= miss_f;

13:48 <ysionneau> so itlb_exception is raised only when the instruction is in the X stage :)

13:48 <ysionneau> so pc_x should be, in theory, the address of the instruction whose fetch caused the exception

13:48 <ysionneau> so I should fix the documentation :)

13:49 <ysionneau> I should have paid attention to the "_x" suffix =)

13:54 <stekern> ah, I didn't even look further up in the file, I just assumed it "has to be" the case =P

13:58 <GitHub132> [migen] sbourdeauducq pushed 1 new commit to master: http://git.io/QHjYHw

13:58 <GitHub132> migen/master 61b8958 Nina Engelhardt: fix synthesis translate on/off switch