09:30 <mumptai> hi

09:30 <mumptai> I'm currently pushing around parts on a pcb design

09:31 <mumptai> small spartan6, some periphery and memory

09:32 <mumptai> and i'm not really sure about the choice between external sdram and (fast) sram

09:32 <mumptai> memory capacity would be sufficient with both

09:32 <ysionneau> if sram chips aren't too much expensive, maybe use sram chips?

09:32 <ysionneau> it's really easier to control, and faster

09:33 <mumptai> but speaking bus&cpu wise, how "bad" is the added latency of the sdram?

09:33 <ysionneau> dunno :/

09:34 <mumptai> the sram is actually cheaper

09:34 <mumptai> but it also requires a fair a amount of power (but so does the old sdram)

11:15 <sb0> murphy doesn't want to go away. all mixxeo boards have been incorrectly fitted with the extra-sluggish -2 slowness grade of slowtan6

11:16 <sb0> this sounds like a lot of upcoming fun trying to meet timing with the ise shitware

11:28 <larsc> fun

11:31 <sb0> other than that, they look good so far. two are completely assembled and the power supplies are OK.

11:33 <larsc> good

11:34 <GitHub18> [migen] sbourdeauducq pushed 6 new commits to master: http://git.io/9CNDRw

11:34 <GitHub18> migen/master 1209ec1 Sebastien Bourdeauducq: actorlib/fifo: rewrite...

11:34 <GitHub18> migen/master 71b14ac Florent Kermarrec: actorlib: add fifo

11:34 <GitHub18> migen/master 87a68ec Sebastien Bourdeauducq: examples/basic/namer: cleanup

17:53 <larsc> hm, what's typically the default pin configuration after power on reset, before loading the bitstream for xilinx fgpas?

19:22 <Hawk777> larsc: tristated or pull-up, depending on the state of the HSWAP_EN pin

19:35 <larsc> thanks