lekernel changed the topic of #milkymist to: Mixxeo, Migen, Milkymist-ng & other Milkymist projects :: Logs: http://en.qi-hardware.com/mmlogs
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<lekernel> this is from a xilinx appnote: http://pastebin.com/PALtwn3B
<lekernel> yes, "assign mdatain = datain;" would work just as well
<lekernel> (the same appnote uses "=" for interblock communcation and "<=#1" in many synchronous assignments ...)
<davidc___> lekernel: some people do the rediculous <=#1 so it looks pretty on their waveform viewers
<davidc___> (or because they don't know how nonblocking assignments work)
<lekernel> judging from the general quality of this appnote, I'd rather believe the latter theory
<lekernel> from the same talented author, this 4-bit counter is also worth seeing: http://pastebin.com/AvKiEkNZ
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<davidc___> ps lekernel - the current SyncFIFO impl definitely won't map to BRAMs in an s6
<davidc___> or at least won't in the situations I've tried
<wpwrak> that's why gigabyte-sized memories were invented. so that we can count to 32 bits and some day even beyond.
<lekernel> davidc___, ok, feel free to send a patch. I haven't used sync FIFOs so large that this would become a problem.
<lekernel> davidc___, and you know that Xst only attempts to use BRAM beyond a certain memory size, right?
<davidc___> lekernel: 4kbyte fifo :)
<davidc___> lekernel: It maps to BRAM fine as an asyncfifo, or with that interlock patch from before
<davidc___> lekernel: I'll add a bypass path (for latency=1) and resubmit
<lekernel> ok. but we can't increase FIFO latency, one needs to be radical about performance when targeting slowtan6
<davidc___> yeah, a bypass will do the trick.. and pfft.. S6's are so much faster than S3s... its like living in a dream world
<davidc___> I haven't had to resort to laying out manually LOC'ed LUTS/PRIMS once yet this design!
<lekernel> they're horribly sluggish compared to what nvidia does
<lekernel> period :)
<davidc___> lekernel: er compared to nvidia GPU ASICs? :)
<lekernel> even the s6 hard blocks are slow... look at the SERDES
<lekernel> nvidia GPU can use DRAM at 5Gbps/pin
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<GitHub26> [milkymist-ng] sbourdeauducq pushed 1 new commit to master: http://git.io/n_IvVg
<GitHub26> milkymist-ng/master ea05031 Sebastien Bourdeauducq: add DVI output
<lekernel> yay, digital video out through the DVI port works now
<lekernel> I can't believe this board doesn't seem to need any green wire
<GitHub54> [milkymist-ng] sbourdeauducq pushed 1 new commit to master: http://git.io/K5KAbw
<GitHub54> milkymist-ng/master 1672c4a Sebastien Bourdeauducq: framebuffer/dvi: minor fixes
<davidc___> lekernel: don't jix it ;)
<davidc___> lekernel: Also, I think the SyncFifo could be 0-cycle-latency if you wanted
<davidc___> lekernel: if that'd help performance
<davidc___> (right now it's one - sync write to SDRAM, ASYNC read)
<davidc___> when level == 0 you can just connect din to dout and cross-connect writable/re readable/we
<davidc___> (dunno whether the comb logic that uses the FIFOs is safe with that though)
<lekernel> it would functionally work, but not meet timing
<davidc___> Yup; definitely stretches out the timing path.
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<lekernel_> it would functionally work, but not meet timing
<lekernel_> in fact, the only reason why I have inserted the FIFOs in the SDRAM controller is to break long timing paths
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<davidc___> lekernel_: gotcha. Any bypass would bring those paths back again, so it pretty much _has_ to be an async-read
<davidc___> (IE, no brams).
<davidc___> Would a tuning parameter for the SyncFIFO be ok?
<lekernel_> no, you can register after the bypass
<lekernel_> you only need a mux in the output
<lekernel_> and all that mux's inputs can be outputs of registers
<lekernel_> directly
<lekernel_> in case there are still difficulties meeting timing with that mux, a tuning parameter would be welcome indeed
<lekernel_> but if timing works, then KISS
<lekernel_> and YAGNI
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