07:40 <barmstrong> Howdy! I'm trying to build migen's vpi module on OSX, but I'm having issues on the migensim.vpi step http://pastebin.com/1H4A8E3k

07:41 <barmstrong> I don't know where these symbols are supposed to come from. It looks like I'm not including some library directory?

07:44 <barmstrong> I'm very excited to try migen out, and I've converted my module to verilog successfully. I would love to get simulations working :)

14:28 <sb0> so, HDMI seems to work with minor problems

14:28 <sb0> first the HPD control (simulating port connection/disconnection under FPGA control) doesn't work reliably

14:29 <sb0> second, the PLLs attempt to lock and generate random signals when you put them out of reset without a stable input clock present. I guess that's a new "feature" of the stepping 4 slowtan6 silicon, and should be an easy fix

14:30 <sb0> looking at #1 ...

14:32 <sb0> otherwise, EDID and HPD readout work reliably, and I haven't found problems yet when a proper video signal is applied before PLL lock

14:32 <sb0> haven't tried more than 35MHz pixel clock (350Mbps/lane) yet, though

14:35 <sb0> hmm, for solving #1 we might have to switch off the 50 ohm terminations to 3.3V to simulate a full disconnection. maybe some GPUs use that instead of the designated HPD pin to detect port connection ...

14:43 <larsc> how long do you pulse?

14:43 <larsc> a short pulse signals an updated edid

15:10 <sb0> several seconds

15:10 <sb0> and one of the problems is, if you plug a cable while the FPGA is supposed to hold HPD low, it is sometimes detected

15:10 <sb0> I have not measured the HPD voltage yet, but that's the logical next step

15:12 <sb0> very bad mixxeo picture: http://imgur.com/Q9La7XT

20:40 <GitHub10> [milkymist-ng] sbourdeauducq pushed 1 new commit to master: http://git.io/Ga8ClQ

20:40 <GitHub10> milkymist-ng/master dba6189 Sebastien Bourdeauducq: dvisampler: add HPD registers