Lofty changed the topic of #prjmistral to: Project Mistral: Yosys (and hopefully nextpnr) on Cyclone FPGAs - https://github.com/ZirconiumX/mistral - logs: https://freenode.irclog.whitequark.org/prjmistral
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<Sarayan> Et Lofty, are you bored?
<Sarayan> Hey
<Lofty> Yep
<Lofty> Very much so
<Lofty> What can I do for you, Sarayan
<Lofty> ?
<Sarayan> Starting line 104 you have all the muxes that control the dsp behaviour
<Sarayan> format is mux_name:bits [list of bit positions]
<Sarayan> value name-of-the-selection
<Lofty> Holy shit, wow
<Lofty> That's...quite a bit
<Sarayan> the amusing question is understanding what the muxes actually do
<Sarayan> there's a bunch on labs and m10ks too :-)
<Sarayan> I just finished transcribing that one is all
<Sarayan> I remember you were wondering about of the dsp worked, well, it's more information to think about it :-)
<Sarayan> we'll have to document it at some point, at least enough to make synthesizing for it viable
<Lofty> mwk: ^
<mwk> ... heh
<mwk> sounds fun
<Lofty> There are...quite a few inverters here, actually
<Sarayan> yeah, they have inverters on the clocks usually, neg_edge here I come or something
<Lofty> Hahaha
<Lofty> Well, if a rumour holds true, the PIPs in Intel chips are inverting
<Lofty> So that might be a hardware hack to deal with reaching somewhere with an inverted signal
<Sarayan> Probably going to write a probe which takes a rbf and a bel coordinate and give you the state of the muxes
<Sarayan> I don't really want to put the intel names in public code though
<Sarayan> I know the LUTs are stored inverted
<Lofty> Yep
<Lofty> That...seems to be quite common
<Sarayan> also, lots of connections are two bits, so double inverter?
<Sarayan> an interesting detail, you may have noticed that in the chip planner there are no bels starting at (45, 37) all the way to the right
<Sarayan> ever cuts in the middle of columns 45 to 50
<Sarayan> well, I don't know if the bels are there or not, but the associated routing is
<Sarayan> they're probably not working though, used the space for the arm border or whatev'
<Lofty> Hmmm...
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<Sarayan> Lofty, still around?
<Lofty> Aye
<Sarayan> Needs posix/linux/*bsd, hopes it compiles for you
<Sarayan> compiles with make into a fmaker program
<Sarayan> fmaker without parameter gives you the help
<Sarayan> model gives you the list of supported models (only one for now)
<Sarayan> bel gives you the list of bels and they tile positions for a given model
<Sarayan> tile model x y gives you the mux status for the bel in the tile (except for m10k, but lab, mlab and dsp is in there)
<Sarayan> for lab.mlab is only the global state
<Lofty> > -O9
<Sarayan> tile model x y i gives you the state for labcell number i
<whitequark> :/
<whitequark> don't use -O9 folks
<Sarayan> (bad) habit
<Lofty> If you really want performance, please use -flto, Sarayan
<Sarayan> I know, I should use -O3
<Lofty> -O3 -flto
<Sarayan> Took this habit when gcc added -O2 then -O3, hard to get rid of it
<whitequark> they should just make it a hard error imo
<whitequark> and *especially* things like -O10
<Sarayan> also, there's a little too much stuff coming directly from quartus in there (mux names, etc) so keep it low profile for now, heh?
<Sarayan> anyway, you can play with that and the chip planner to try and understand all the muxes
<Sarayan> I'll add m10k next week
<Lofty> It always amuses me that the first chip we picked was the one in the MiSTer, even though it's got an ARM SoC on there
<Sarayan> I pixked it *because* it's in the mister
<Lofty> I think whitequark's chip should be next - can't remember what it is though
<Sarayan> wq's isn't open source already?
<Lofty> It's a different SKU
<Lofty> Uh, DE0-CV
<Sarayan> it's a Cyclone V?
<Lofty> 5CEBA4F23C7
<Lofty> She needed a dev board for nMigen's Intel backend, I think?
<Sarayan> Ah, A4, different die
<Lofty> 5CEBA4, not 5CSEBA6
<Sarayan> EB and A4, very different die :-)
<Sarayan> Well, I'm building it to make it usable across the cv models
<Sarayan> prolly won't try outside of cv though
<Lofty> I dunno, it's worth experimenting a bit
<Sarayan> well, have fun with that toy, I'll be gone for the next 3 days
<Sarayan> oh, thre's a fuckup or two in the unframing of rbf files, the righmost tiles are broken somehow
<Sarayan> I'll fix that whenever
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<Sarayan> did it compile for you btw?
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<Lofty> It did, yes
<Sarayan> cool
<Sarayan> have fun then :-)
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<Sarayan> ok, wq's die is the e50f
<Lofty> Sounds about right
<Sarayan> and the model e50b
<Lofty> At least we know how the die naming system works
<Sarayan> we do?
<Sarayan> I just run a synthesis and see with files are dumped :-)
<Sarayan> ok, I've added the m10k after all, so I updated fmaker.zip
<Sarayan> and it's bedtime, and biking for three days, so see you much later
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