<azonenberg>
to cost-down you can DNP one of the AFE+ADC boards to make a 4 channel scope
<azonenberg>
The AFE+ADC boards would mate to the FPGA board via a samtec q-strip
<Degi>
Hm that sounds nice.
<azonenberg>
In a 1U headless form factor
<azonenberg>
The next model up will be the same AFE, essentially, but with a higher bandwidth AA filter at maybe 250-300 MHz, and an ADC dedicated to each AFE
<azonenberg>
So the 8 channel scope would have 8 ADCs
<azonenberg>
possibly move to a kintex7, TBD - i havent crunched numbers on package size or fpga resources needed to support that many lanes
<azonenberg>
The AFE+ADC boards would be in a PCIe x4 half height form factor, with LVDS over the PCIe data pins
<azonenberg>
not using PCIe protocol, just the connector
<azonenberg>
the full system would be 2U high with up to eight ADC+AFE cards. If I go with a kintex7 i can do 10GbE on it
<Degi>
Oh neat
<electronic_eel>
maybe add 8 or 16 digital inputs to the higher model as well, then you really have enough inputs in parallel
<azonenberg>
or even 40G
<azonenberg>
electronic_eel: Yes, we could easily make a digital input card too
<azonenberg>
probably using the frontend i was designing for starshipraider
<azonenberg>
Degi: anyway, the next model past THAT will be using the LM97600 (1.25/2.5/5 Gsps interleavable, 1-4 input, 7.6 bit)
<azonenberg>
probably two variants of that just like the HMCAD1520 version: a one-adc-per-4 channel and one-adc-per-channel
<Degi>
Huh that ADC is pretty cheap for 5 GS
<azonenberg>
Yes, exactly. Low ENOB but for SI work often you dont need a ton of sample rate to see how open the eye is, etc
<azonenberg>
Then the endgame is one AD9213BBPZ-10G per channel: 10 Gsps 12 bits JESD204B :D
<azonenberg>
8 of those and you're competitive with an upper midrange pro scope like the lecroy hdo8108a
<Degi>
Is the development planned in that order?
<azonenberg>
Roughly yes, working our way up in bandwidth
<Degi>
Nice
<Degi>
My current plans are an ECP5 direct streaming the samples over PCIe (it has a few MBytes internal buffer though). I think that would make sense as an entry level board too.
<azonenberg>
All designs will be open source although i intend to sell assembled units with calibration etc
<azonenberg>
Maybe we can share the AFE+ADC board and just swap in different digital subsystems?
<Degi>
I think the PCIe cards could have the same interface for the AFEs
<azonenberg>
exactly
<Degi>
yeah
<azonenberg>
anyway, in parallel with all this i have FREESAMPLE
<Degi>
I saw that project, it kinda looked unfinished though (or my kicad is broken)
<azonenberg>
all it will do is eye patterns, but with crazy high resolution
<azonenberg>
as long as you don't mind waiting 10+ minutes to get one
<Degi>
Hm how exactly does that work? Does it set a 16 bit reference voltage and then check when the input voltage goes above that?
<azonenberg>
So, you know how a flash ADC works right?
<Degi>
Hm its the one with a lot of parallel comparators?
<azonenberg>
yes
<azonenberg>
then a successive approximation ADC basically is a binary searched time-shared equivalent
<azonenberg>
rather than evaluating every one of the 2^n decisions at once, you do one at a time and binary search
<Degi>
So like you need 2^16*sample_length of samples to get a trace?
<azonenberg>
I'm getting there :)
<Degi>
:9
<Degi>
*:)
<azonenberg>
Another, stupid, option is a linear searched version
<azonenberg>
basically, drive one input of the comparator with a triangle wave
<azonenberg>
record the code when it tripped, that's your sample value
<azonenberg>
repeat for the next point in time
<azonenberg>
Ultimately, all of these are acquiring a 2D matrix with codes on the Y axis and time on the X axis
<azonenberg>
filling in each element of the matrix with a boolean value, then calculating output codes
<azonenberg>
Some, like SAR, are smart and only evaluate some elements, producing a sparse matrix
<azonenberg>
others, like flash, throw hardware at the problem and evaluate a whole column at once
<azonenberg>
But you see how they're all collecting ~the same data?
<Degi>
Hm yes
<azonenberg>
So, the problem with the linear searched variant is that your comparator and dac have to run at 2^n times the sampling rate
<azonenberg>
Which means it's slow
<Degi>
(Also does that project really use an 8 layer PCB or is that just a kicad thing?)
<azonenberg>
SAR reduces this to N times, but it's still slow
<azonenberg>
(really 8 layer)
<azonenberg>
anyway, so what freesample does is transpose the matrix :D
<azonenberg>
You sample the entire waveform with the dac at one code
<Degi>
Ah yeah
<azonenberg>
then go back in time, bump the dac, repeat
<azonenberg>
now you need a comparator at the full signal bandwidth and a slow i2c dac
<azonenberg>
fast comparators are cheap
<azonenberg>
the whole rest of the design is triggering, CDR, and other stuff needed to make sure each 'scanline' of the waveform is in sync with the rest
<azonenberg>
also, rather than sampling the whole waveform at once - which would require a 1 Tsps SERDES on the comparator output
<Degi>
Hm so it gets triggered, then after x delay compares the input with the DAC value?
<azonenberg>
i use a latching comparator and adjust trigger delay on the latch
<azonenberg>
then i can sample the latch output at my leisure in a nice slow clock domain on the FPGA
<azonenberg>
So basically i sweep phase delay on the PLL + external delay line to select the X axis, the DAC code to select the Y axis
<azonenberg>
then at each (x,y) i collect a bunch of samples and average them
<Degi>
And that makes a boolean value for that spot
<azonenberg>
This gives me the probability of the signal at time X being less than Y
<azonenberg>
Which, in math terms, is the cumulative density function (CDF) of the signal, modulo the unit interval
<azonenberg>
If you take the partial derivative wrt voltage, you get the probability density function
<Degi>
Which makes a nice eye diagram
<azonenberg>
If you render the 2D PDF as a grayscale image, you get an intensity graded eye :D
<azonenberg>
exactly
<azonenberg>
So i am literally measuring the partial integral of the eye pattern natively
<azonenberg>
then differentiating in postprocessing
<azonenberg>
I built a TDR at 40 Gsps using this architecture for a consulting gig years ago, building on top of a previous 1.25 Gsps version that did not do the phase delayed latch sampling (it sampled the comparator directly with FPGA inputs)
<Degi>
Hmm depending on how fast you can adjust the delay and reset the comparators, a few minutes seems excessive
<azonenberg>
freesample is the logical conclusion with a clock recovery trigger
<azonenberg>
So that's the beauty of the architecture
<azonenberg>
you can trade timebase and voltage resolution, and noise, off against WFM/s
<azonenberg>
less averages and less points = faster acquisitions
<Degi>
Oh sampling a comparator with a DAC lol
<azonenberg>
my plan is to start sampling like 128 DAC codes and maybe 100ps timebase
<azonenberg>
then gradually fill in over time
<azonenberg>
so you get a rough view of the eye right away and it slowly becomes more detailed
<azonenberg>
like a progressive jpeg
<Degi>
Hm are you planning on using serdes inputs for the comparator output?
<azonenberg>
Not necessary. It buys you slightly higher sampling rate, but the latch+PLL architecture gives me 1 Tsps sampling rates with ~2ps jitter
<azonenberg>
you cant get that with a serdes. or eve close
<azonenberg>
using a serdes you'd max out at ~10 Gsps
<azonenberg>
at which point you're not really any better than a realtime scope
<azonenberg>
i'll be using a plain old lvds gpio at maybe 250 MHz
<Degi>
I meant just for the last part where it gets sampled to the FPGA. Of course the PLL delay makes sense for higher sample rates
<azonenberg>
I do plan to make a serdes based *logic analyzer* though
<azonenberg>
something akin to the lecroy HDA125, a fair number of channels at 12.5 Gsps
<azonenberg>
anyway, on top of all of this we're also working on a wideband transmission line probe. So far i've characterized prototypes out to 2 GHz and sonnet sims say it should have -3dB cutoff somewhere around 10 GHz
<azonenberg>
this is the current pcb rev, the tip socket is being redone in a final board spin
<azonenberg>
It fits the same PMK tips and ground accessories as the PMK Tetris active probes, better known as the LeCroy ZS series
<Degi>
Hm FREESAMPLE also sounds relatively cheap parts-wise, maybe 300 €? Well, the comparators are kinda pricy.
<azonenberg>
No, the 3ps delay line is probably around $300 alone
<Degi>
Oh
<azonenberg>
it's a $1K range project at least
<Degi>
Didn't look at that part yet...
<azonenberg>
that said, you can get samples of it :D
<azonenberg>
a lot of the BOM is sample-able
<Degi>
Oh neat
<azonenberg>
so for a one-off it could be a lot cheaper
<azonenberg>
But right now it's on hold while i practice more at lower speeds. I don't want to spend all that money and have it not work
<azonenberg>
so i want to be absolutely certain i know what i'm doing
<azonenberg>
anyway, are you familiar with libscopehal / glscopeclient?
<Degi>
Hm yes, the HMC856 is like 200 € on mouser. oof
<Degi>
No not really
<azonenberg>
Basically libscopehal is an open source VISA replacement, drivers and interface code for all sorts of test equipment
<Degi>
I kinda get that feeling at the whole oscilloscope project... Like a small mistake in PCB design could mean having to desolder the pricy stuff and reball BGAs and hope that it works...
<Degi>
What is VISA?
<azonenberg>
libscopeprototocols is the companion collection of protocol decodes
<azonenberg>
national instruments's awful data acquisition library
<azonenberg>
i'm not even trying to be api compatible etc, just solving the same problem they do
<azonenberg>
anyway, then glscopeclient is the GUI around all of this
<azonenberg>
This example is combining an FPGA internal logic analyzer with an external scope. Multi-scope sync is possible but all of the trigger configuration and skew compensation is manual right now, there will eventually be a wizard telling you e.g. "touch a probe from scope 1 and scope 2 to the same point" and it will null out the delay of the trigger signal between them, etc
<azonenberg>
And yes, a small mistake will definitely mean lots of wasted hardware
<Degi>
Hm so I can send a bunch of samples and some metadata to the program for it to display a waveform?
<azonenberg>
Yes. And it's a full realtime UI that can control the scope too
<azonenberg>
it's explicitly meant for headless operation
<azonenberg>
Both of those used my LeCroy WaveRunner 8104
<azonenberg>
Which is now an 8104-MS (had the logic analyzer retrofitted by the factory)
<Degi>
Oh neat it makes eye diagrams from a stream of samples
<azonenberg>
I also have a HDO9204, the two are my main workhorse scopes
<Degi>
Huh that's a fancy scope
<azonenberg>
Yeah. but if you wanted to, you could make a "scope" driver that spits out eyes directly, bypassing the protocol decode
<azonenberg>
which is what freesample will do
<azonenberg>
The point is, glscopeclient can do all of this as long as your scope has the bw/sample rate
<Degi>
Do you yet have any plans for a pinout on the basic scope AFE connectors?
<azonenberg>
you can do usb protocol decode on a cheap rigol :D
<Degi>
Hm hook up an ECP5 over USB3 and decode USB2 haha
<azonenberg>
My tentative plan is to have the AFE + ADC on a single board, once i've characterized the AFE in isolation i'll re-layout with the ADC attached
<azonenberg>
then have a QTH-030 or QTH-060 to connect to the FPGA board
<Degi>
With AFE I meant AFE+ADC (is there another name for that combo?)
<azonenberg>
providing +12V power (regulating to all lower voltages on the analog board), a bunch of i2c/spi control signals, and 8 lanes of LVDS coming off the ADC
<Degi>
Acquisition board is good, I think tektronix uses that
<Degi>
Hm why regulate on board?
<azonenberg>
well some of them are low voltage references i'll create as i need
<azonenberg>
the rest i want to regulate near point of load to reduce drop
<Degi>
For example the LVDS driver voltage
<Degi>
Ah that makes sense
<azonenberg>
remote sense with multiple endpoints is hard
<azonenberg>
I might supply an I/O rail
<Degi>
Hm maybe add a 5 V or so, then linear regulators could be used, saving money/board space
<azonenberg>
but the +/- 5V and +/- 6V analog rails etc will be derived as close to the boards as possible
<azonenberg>
My plan is to DC-DC the 12V down to +/- ~7 then LDO from there
<azonenberg>
exact intermediate rail is TBD, but i want enough headroom for the LDOs despite some drop in transmission
<Degi>
The HMCAD1511 uses +1.8V only, right?
<azonenberg>
i might have the FPGA board take in 12V then supply the lower voltage rail to the acquisition boards, TBD
<Degi>
12V is good, PCIe also supplies that (and I guess everybody has 12V adapters laying around)
<azonenberg>
The HMCAD15xx take 1.8V for analog and digital core, then the digital input rail is variable 1.8 or 3.3
<Degi>
Also does the HMCAD1511 only have 350 mV pk-pk LVDS swing or am I reading the datasheet wrong?
<azonenberg>
i'll likely have separate io and analog 1.8V rails
<Degi>
Yes, otherwise it'll be a bit noisy
<azonenberg>
It does seem to suggest 350 mV differential
<Degi>
Well my current DDR FPGA experiments were with 5 V pk-pk differential swing at the transmitter... But I guess 350 mV is enough too
<azonenberg>
Anyway, i'm not worrying about the ADC subsystem right now
<azonenberg>
The AFE board is intended to produce HMCAD15xx compatible output levels
<azonenberg>
and that will be enough for the purposes of testing
<azonenberg>
we have a bunch of stuff to worry about like input protection, frequency response, flatness across various gain steps, etc
<electronic_eel>
Degi: your plan is to not trigger and then sample to ram, but continously sample and transmit via pcie into the pc?
<Degi>
Yes
<electronic_eel>
that would allow software triggers, like trigger on a math channel or similar
<azonenberg>
Or on a protocol decode
<Degi>
I also wondered if its possible to make high impedance inputs like an ordinary oscilloscope. I mean the HMCAD1511 has 4 channels, maybe 1 or 2 could be high Z
<azonenberg>
Degi: so i thought about that
<Degi>
Or a really long fourier transform
<azonenberg>
the thing is, the old school R-C passive probes are just all around terrible
<Degi>
True that
<azonenberg>
i consider them deprecated, and have no intention of supporting them
<azonenberg>
IMO the way forward is transmission line probes for most purposes, and active probes if you really need high Z
<Degi>
But sometimes you want to sample low frequency stuff at high impedance and maybe high voltages. Would an active probe be better there?
<azonenberg>
I have plans to make a fairly wideband low cost active probe
<azonenberg>
The LMH3401 is begging to be turned into one
<azonenberg>
7 GHz -3dB bw, extremely flat to 2 GHz
<Degi>
Yeah high Z inputs on the scope aren't really usable above 100 MHz or so...
<azonenberg>
And it's... $15 or so?
<Degi>
Oh that thing turns a single ended 50 ohm to differential signal with only 2 external resistors to match the transmission line?
<Degi>
I think I'll go to bed soon, it's almost 2 AM here
<azonenberg>
pretty much. I'd need some kind of twinax on the output though, which isn't ideal
<azonenberg>
or i could try to balun to single ended
<azonenberg>
details TBD
<Degi>
Hm you could glue two coaxes together
<azonenberg>
But it's cheap enough i've thought about making solder-in "disposable" active probes lol
<Degi>
Well I wouldn't consider that that cheap lol, unless you're working on some super fancy device...
<azonenberg>
have you seen how much scope vendor active probes cost? :p
<Degi>
RIP
<azonenberg>
or THEIR solder in probe tips?
<Degi>
They have that?
<azonenberg>
Yes
<azonenberg>
With four digit price tags for a couple of them
<Degi>
Hm something like an inline RF probe could be useful too.
<azonenberg>
inline you mean a T that steals a bit of the signal?
<Degi>
Yeah
<Degi>
Or maybe just a high Z input OP amp connected on the transmission line (though that could cause some reflections)
<miek>
i just terminate the negative out and ignore it on the lmh3401 :p
<azonenberg>
i already have those for ethernet, HDMI, and USB 1/2 (although the USB one in particular needs some work)
<azonenberg>
miek: thats an option too
<azonenberg>
Degi: i dont have one for generic RF signals but it would be trivial to build
<Degi>
Huh neat
<azonenberg>
I also have a copy of the Sonnet field solver (L2 Basic, planning to upgrade to silver/gold eventually) which has been quite handy for modeling some of this stuff
<Degi>
I wonder if the cards for the small oscilloscope could also be fitted with DACs, especially when they have 2 card slots. Then circuit responses could be measured. Or as a digital signal generator...
<azonenberg>
yes that's reflection from each end (slightly different due to the shape of the transition, so it's not quite a reciprocal network)
<Degi>
Hm having a HMCAD1511 and some 1 GS/s 8 bit DAC would have the upside that both can work at the same time, since PCIe 2.0 x4 has 20 Gbit/s in each direction. (A potential application could be NMR, though there HMCAD1520 may be more useful)
<azonenberg>
Well, making a pin compatible dac card shouldn't be too hard
<azonenberg>
we could have a generic chassis and load one or the other
<azonenberg>
or two of one, or two of the other
<azonenberg>
you'd likely need a new bitstream but that's not a huge deal
<Degi>
I think for the ECP5 the differential pairs can be used as IOs, so no reconfiguration necessary. But yes, otherwise just make bitstreams for each configuration
<azonenberg>
7 series LVDS at least have bitstream switchable on die termination, so you dont have to worry about discrete 100R resistors at one end of the board or the other
<azonenberg>
i dont think its runtime switchable though
<Degi>
What do you plan as the language for the gateware?
<azonenberg>
Systemverilog is my usual preference, which unfortunately prevents use of symbiflow until they add enum and struct support
<Degi>
ECP5 also has bitstream settable termination
<azonenberg>
i dont use a lot of SV features so yosys is most of the way there
<azonenberg>
enums and structs are the only things it's missing last i checked
<Degi>
Hm I think for the PCIe part I'd use nMigen
<azonenberg>
Anyway, if you want to build a different fpga subsystem that's fine by me, I think most of the work is going to be in the analog side anyway
<Degi>
Yes
<Degi>
Hm also why 100 MHz bandwidth and not 400 MHz? (As far as I know, Sin x/x is good till Fsample/2.5)
<azonenberg>
Because I'm optimizing the current board for the 4-channel use case
<azonenberg>
so 250 Msps 8-bit / 160 Msps 12-bit per channel
<Degi>
Would it be a good idea to make one channel 400 MHz? (Or maybe even switchable with a RF switch like the USB switches)
<azonenberg>
100 MHz seemed like a reasonable compromise. It's what most of the cheap rigol scopes using the HMCAD use
<Degi>
Oh they also use that IC
<azonenberg>
the 1511, not the 20, but yes
<azonenberg>
(12 bit is currently unheard of in entry level scopes)
<azonenberg>
My plan is to have 250-400 MHz bandwidth in the one-adc-per-afe variant
<azonenberg>
Since that will do 1 Gsps 8bit / 640 Msps 12-bit
<electronic_eel>
I think a switchable filter wouldn't be that hard, and would improve the 1ch and 2ch usecase
<azonenberg>
Put some thought into how to do that then, while i work on other parts of the design?
<Degi>
Depending on your price range, USB 3.0 switches (one is enough to switch between two differential pathways) are like 2 € (otherwise RF relays 2*15 €)
<electronic_eel>
yes, I can think about that. but not now, as with Degi it is 2am here, so I'm going to bed soon
<azonenberg>
Enjoy. it's 18:00 here but i have other stuff to do that isn't oscilloscope design
<Degi>
Same, good night!
<electronic_eel>
Gute Nacht Degi :)
<Degi>
Gute Nacht :)
<Degi>
Just noticed that a storage oscilloscope with the ECP5 internal ram would be rather feasible, it has tens of MB of that and like 50 or so differential pairs, so it could sample like 6* HMCAD1511 with 1-2 MS sample depth
<azonenberg>
tens of megabytes of ram???
<azonenberg>
the LFE5UM-85 is 3744 Kbits of total embedded ram
<azonenberg>
or 468 KB
<azonenberg>
I'm sitting across the lab from a virtex ultrascale+ devkit with an FPGA that digikey sells for $50K and only has 270 Mb (33 MB) of large-block ram
<zigggggy>
azonenberg are you shut down yet?
<azonenberg>
zigggggy: define "shut down"
<zigggggy>
no one in the office.. no one in the factories.. no one in your side gigs to talk to
<azonenberg>
The office has been empty for a while now, we're running full speed ahead remote though
<azonenberg>
Work is actually planning on mailing some client hardware to me to work on at home - there's nothing i can do in their lab there that i can't do in the setup at home, so i expect to remain at ~100% productivity
<zigggggy>
what happens when you run out of food
Degi has quit [Ping timeout: 246 seconds]
Degi has joined #scopehal
<sorear>
remember pnw is a couple weeks ahead of the rest of the country
<azonenberg>
electronic_eel: oh you know what else will help?
<azonenberg>
the comparator trips at 5V *before* the attenuator
<azonenberg>
but the diodes don't start clipping until 5V *after* the attenuator
<azonenberg>
Which is 10V before
<azonenberg>
So as the input is ramping up from 5V to 10V, the comparator is already starting to open the relay
<_whitenotifier-3>
[starshipraider] azonenberg pushed 1 commit to master [+1/-0/±9] https://git.io/JvXrc
<_whitenotifier-3>
[starshipraider] azonenberg e046d2b - Continued work on AFE characterization board
<azonenberg>
D3/D4 are going to be halves of a NUP1301U, i just havent drawn the sch symbol for it yet
<monochroma>
hmmm i assume U2B will be put in in shutdown mode when not in use ?
<monochroma>
looks like B's enable pin share the same net as A's enable, i would probably break that out so the B amp isn't amplifying noise and such while not in use
<azonenberg>
Fair enough
<monochroma>
looks pretty nice other than that
<azonenberg>
ok so i picked out exact passives for the AA filter, hooked up the proper protection diode
<azonenberg>
I think this makes the input stage done
<azonenberg>
Added decoupling to the offset stage, which i think is now done too
<azonenberg>
Still have to do all of the stuff for configuring the gain stage but the signal path is done
<azonenberg>
Then the common mode shifter and final gain stage is nonexistent right now, as is the PSU, DAC for controlling offset, and the MCU subsystem
<azonenberg>
Still a fair bit more work to do :)
<Degi>
Hm so you have a relay at the input which turns off in case overvoltage is detected?
<Degi>
Also maybe in the relay driver section, have a higher valued zener, to turn the relay off faster.
<Degi>
Hm the relay doesn't seem to be rated for more than 0.5 A switching current (so the relay might be damaged if for example 50 V are applied and it switches off).
<electronic_eel>
Degi: I also suggested using a higher zener, but he wanted to keep the fet (because he also uses it on other parts), and this fet just goes to 30v
<electronic_eel>
another thing I just saw is to add protection for the lm393 inputs in the power off state
<electronic_eel>
if you apply power to the input when the whole device is off, current will flow through the vin-divider to vin_div10, and from there through the esd diodes of the lm393
<Degi>
Hm doesnt it have a 9k resistor in series
<electronic_eel>
if you connect the 50v?
<Degi>
Thats like 6 mA
<electronic_eel>
just a cheap bat54s to -5 and +5 should suffice
<Degi>
Hm in that state, isn't the relay off anyways?
<electronic_eel>
yes, but vin is taken from before the relay
<Degi>
Ah right
<electronic_eel>
that is good as it is, as you can detect when the overload is removed
<Degi>
Hm are the input protection diodes good enough for 100 MHz bandwidth?
<electronic_eel>
also don't switch on when you see overload
<electronic_eel>
NUP1301U - they won't be a problem for 100MHz
<Degi>
I see, 0.6 pF
<electronic_eel>
I said BAV99 should be enough for 100MHz, but the NUP1301U offer a lot more margin
<Degi>
Maybe on page 5 of the datasheet, connecting R11 to a FPGA pin instead of 5V0_P would make sense, to be able to turn it off
<electronic_eel>
maybe not the fpga, but the microcontroller responsible for talking to the dac and stuff
<Degi>
Hm is that really necessary? I mean you could have a SoC on the FPGA itself (that'd save money, on the other hand, µC's arent that pricy either)
<electronic_eel>
I think the connectors are expensive, so you want less signals running over them. having a uart to the analog board makes that easy
<Degi>
Ah the analog board itself has a µC
<electronic_eel>
yes, a small one
<Degi>
(On the other hand, the connectors have like 60/120 pins, but yes, having a µC on the board makes a lot of sense)
<electronic_eel>
also makes sense for characterizing and debugging. you just hook up a serial port and can listen in or talk to it
<Degi>
Huh, PCIe electrical spec says that clock signals need to be matched to 0.005 inch, which is like 0.127 mm. Didn't think that it needed to be that tight for a 100 MHz clock...
<monochroma>
PCIe doesn't require a clock
<monochroma>
and that's weird...
<Degi>
I mean the wires within a differential pair
<Degi>
Yes but it provides a reference clock
<monochroma>
ahhh
<Degi>
The problem is I have the ECP5 EVN dev board and that thing uses SMA breakouts lol (so 0.1 mm mismatch could happen easily, though I hope that's not too bad on the data lanes)
<Degi>
I mean that's 660 fs...
<Degi>
At 0.5 c
<electronic_eel>
just bend the wire connected to the smas till it works ;)
<Degi>
Hm I'll use the PCB mounted version of the SMA screw connectors on cables... So I hope the mismatch isn't that big. And on the FPGA side, the signals are terminated to ground anyways, somebody told me that in that case a tiny mismatch isnt that bad
<Degi>
(At least that's what I've understood from what they've told me)
<electronic_eel>
I found pcie to be releatively forgiving to bad cabling and similar problems
<Degi>
I mean LTT made a 3 meter PCIe expander lol
<Degi>
I wonder if I can get this PCIe adapter board routed in 2 layers...
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<lain>
azonenberg: looks good so far @ AFE
<Degi>
Maybe Vin_offset can be set from the Vcm output of the HMCAD1511?
<Degi>
Are the auxiliary signals of PCIe 3.3 V level?
<Degi>
(Yes it is, just needed to dig a bit deeper into the spec...)
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<lain>
I think when companies use individual SMAs for differential signals instead of a differential connector standard, they're just assuming you'll use matched pair, phase-stable SMA cables
<lain>
which are stupidly expensive :|
<lain>
personally I like sata cabling for moving fast diffpairs around
<electronic_eel>
sata cables are cheap, but they probably won't be improved anymore
<electronic_eel>
usb otoh will get further upgrades
<electronic_eel>
and usb-c connectors are more easy to come by than sata
<lain>
true, I have started using usb-c on newer stuff even just as a generic 4-lane high speed port that can carry power + sideband
<lain>
it's a pretty handy, and dense, connector
<Degi>
Hm it goes both ways though, so you'll either need lane rearrangement facilities or some way to label the connector to only plug one way...
<lain>
or use a mux, but yes
<azonenberg>
Degi, electronic_eel: just got up
<azonenberg>
ok so... the MCU is just for the characterization board
<azonenberg>
the actual system will probably just have fpga gpios going over the connector
<azonenberg>
vin_offset is variable, in order to allow you to correct for a DC offset on the incoming signal
<Degi>
Hi
<Degi>
Hm does the Vin add differential voltage? How is the common mode voltage adjusted to the HMCAD?
<azonenberg>
that directly corresponds to the vertical offset knob on a normal scope
<azonenberg>
That's the very last block, cm_shift.sch (which mostly isn't drawn yet
<azonenberg>
It's going to be an LMH6522 that applies 2 dB of gain to VGAIN_P/VGAIN_N coming off of the variable gain block
<azonenberg>
and has Vcm set to 0.9V to match the HMCAD
<Degi>
Hm in this design https://www.ti.com/lit/ug/tiduba4/tiduba4.pdf they're using a OP amp integrator to automatically set that voltage such that the Vcm at the ADC in equals the ADC Vcm
<Degi>
Page 4
<azonenberg>
This is a standalone AFE characterization board
<azonenberg>
This is not intended to be the actual board that goes into the scope
<azonenberg>
i will be doing a re-layout of substantially the same schematic
<Degi>
Ah yes
<azonenberg>
Since there is no ADC, i have no Vcm input to use :
<azonenberg>
:)
<Degi>
So you can adjust the 0.9 V with a pot or DAC?
<azonenberg>
I probably will use Vcm of the ADC in the real system
<azonenberg>
But right now, i want to get as close to the behavior of the real system as possible, so i have a fixed 0.9V bias just to observe behavior
<Degi>
So you're using fancy equipment to characterize the AFE? That's a good idea, also nice that you have that equipment
<azonenberg>
The MCU is also just a dummy for testing. The real system is going to have I2C and SPI buses plus a few GPIOs going from the FPGA over the Q-strip/PCIe connector
<azonenberg>
there's no reason for any kind of smarts or io expansion on the card, the only critical thing is the overvoltage shutdown and i'm using a wired-OR with the comparators there
<azonenberg>
so it will shut down instantly with no interaction from the FPGA
<Degi>
Turns out that I need 4 layer PCB for the adapter board. Not due to being too full, but because 1.6 mm is too thick for 100 ohm differential pairs with a reasonably high gap/width ratio
<azonenberg>
Yes, i actually did that for my scope probe for ~the same reason
<azonenberg>
i'm using grounded coplanar waveguide, but i have a 4L board with ground on 2, signal on 1, and 3/4 unused except for mechanical support
<Degi>
Yeah sadly I can't use anything other than 1.6 mm for PCIe lol
<azonenberg>
500um for a probe wouldnt be sturdy enough anyway :p
<Degi>
Hm jlcpcb has 200 µm for 4 layer stackup
<azonenberg>
my standard is 100 um for 4 layer fast digital stuff
<azonenberg>
500 was better in my case because i was explicitly trying to match a 50 ohm coplanar waveguide to the width of an 0402 passive
<Degi>
Hm kicad differential routing seems to separate the traces to go around obstacles sometimes.
<azonenberg>
yes. Not great, i find myself hand tweaking the layout sometimes
<azonenberg>
or, if a split is unavoidable, using a loosely coupled design so the split doesnt cause as much of an impedance mismatch
<azonenberg>
anyway as far as characterization goes, i have a 40ps risetime pulse generator and a lecroy hdo9204 oscilloscope
<azonenberg>
and a R&S HMC8012 5.75 digit multimeter i can use for DC offset calibration etc
<Degi>
Nice
<azonenberg>
actually two of the meters, and a waverunner 8104-MS, and two HMC8042 power supplies - but that's beside the point
<Degi>
Have you thought about DIYing a pulse generator? There are some old soviet step recovery diodes on ebay which are advertised with 100-200 GHz BW
<azonenberg>
40ps is already >> 100 MHz bandwidth
<azonenberg>
no point
<azonenberg>
it's faster than the risetime on my 2 GHz scope
<Degi>
Hm isn't 100 GHz wave period 10 ps?
<Degi>
For example the KD528A
<azonenberg>
40ps risetime is somewhere around 8-9 GHz bandwidth iirc
<azonenberg>
anyway i do not have a good variable RF signal generator, and my xaVNA is a bit cheap compared to what i want
<azonenberg>
but ultimately my plan is to characterize the afe with full 2-port s-parameters at each gain level
<azonenberg>
oh the other problem, my xaVNA only goes *down* to 130 MHz lol
<azonenberg>
I've been eyeing the PicoVNA which does 300 kHz - 6 GHz
<Degi>
There's also the nanoVNA, advertised at 50 kHz
<Degi>
Of course that isn't gonna be as good as the picoVNA which is 100x pricier lol
<azonenberg>
yeah the picovna also can be properly calibrated
<Degi>
Is there some rule for distance between differential pairs?
<azonenberg>
rule of thumb is at least 3x substrate thickness between any two signals where you're concerned about crosstalk
<azonenberg>
proper procedure is to throw it in a field solver
<Degi>
So if I have 0.2 mm substrate, then 0.6 mm is good?
<Degi>
Right now I have 0.34 mm trace width, 0.59 mm separation and about 1 mm between pairs
<azonenberg>
It meets the rule of thumb, but i think that rule is for something like max 10% coupling (-10 dB S21 between the lines)
<azonenberg>
So if you really care about coupling, you're gonna have to actually model it
<Degi>
Its for PCIe, so idk
<Degi>
Hm this old GPU i have laying around has about 0.4 mm separation. I think I'll lower it somewhat
<azonenberg>
yes but how thick is the substrate?
<azonenberg>
and how long is the coupled length?
<azonenberg>
like i said, the only way to be accurate is to acutally model the coupling. To both halves of the diffpair
<azonenberg>
what you really care about is differential mode noise, not common mode as the rx should filter that out
<Degi>
Yes, by making the pair separation smaller and the space between pairs wider, that should be reduced, right?
<azonenberg>
Yes
<Degi>
Is there a rule of thumb for how far to keep ground planes away?
<Degi>
(Or should I simply put no ground on that layer?)
<azonenberg>
I generally avoid having ground fill on signal layers unless i am explicitly doing coplanar waveguide for my signal lines
<azonenberg>
if you just have ground snaking all over the place you get all kinds of weird effects that are hard to predict, it messes with your impedances, it doesn't really help SI at all
<azonenberg>
best is to have signal on its own layer, then solid ground on the reference plane
<azonenberg>
again, coplanar waveguide is an exception. But you need to calculate the impedances for CPW rather than microstrip that way
<bvernoux>
azonenberg, PicoVNA seems very nice for the Price
<bvernoux>
anything comparable cost > 15Keuros new ...
<azonenberg>
Yes
<azonenberg>
the harmon one looks cool too, i havent made a final decision. one thing in favor of the pico is i can get it sooner and harmon's isnt done
<bvernoux>
I would have bought it if it will go up to 15Ghz ;)
<bvernoux>
or more
<azonenberg>
I don't have the cash right now, but maybe in a month or so
<bvernoux>
yes Hamon ones seems very nice but it seems they will be ready in few years
<bvernoux>
Harmon
<bvernoux>
The good things with modern VNA like PicoVNA is they are small quiet and fast ;)
<azonenberg>
yes. a full sized vna with screen and knobs is an absolute no go for me, i have nowhere to put it
<bvernoux>
my HP VNA is bit slow (about 35s for full S2P 1601pts) and loudy and heavy and huge ;)
<bvernoux>
I do not speak about dynamic range as all new VNA are always > 110dB which is also a must have
<bvernoux>
anyway my VNA is already from 100 to 110dB for such old instrument it is amazing
<bvernoux>
it is very different from the cheap VNA we see like nanoVNA which are often less than 50dB ...
<bvernoux>
but it is not same price and stability also
<azonenberg>
Yeah i am not super trusting of the low range results on my xaVNA
<azonenberg>
the picovna claims 118 dB dynamic range
<bvernoux>
yes it drift a lot
<bvernoux>
the crystal inside is cheat
<bvernoux>
it requires very stable temperature in room and long time before it is stable a bit ;)
<bvernoux>
xaVNA could be heavily improved by just changing the Crystal by a nice TCXO 0.5ppm
<bvernoux>
or even better a VCTCXO
<bvernoux>
it shall be used mainly to tune some antenna
<bvernoux>
for accurate measurement like your probe it is not good enough
<azonenberg>
Yeah
<bvernoux>
as it requires very low noise, big dynamic range and high isolation internally
<bvernoux>
and such cheap VNA have something like 20dB isolation ...
<bvernoux>
it is where lot of guys doing such VNA struggle
<bvernoux>
isolation between ports is very hard with cheap components/hardware and without big shield
<bvernoux>
a good VNA for good measurements on ports (S2P) requires more than 40dB isolation between ports
<bvernoux>
It is why some very good VNA cost > 200KUSD/EURO ;)
<bvernoux>
it is also because it is a very small niche market ...
<bvernoux>
azonenberg, I'm waiting my 26.5GHz SMA connectors they are locked at 100KM of my House by UPS seems to be down with COVID-19 in France :(
<bvernoux>
everyday it is like a sunday in France
<Degi>
Hm the skew values from kicad skew tool seem a tad bit high
<azonenberg>
bvernoux: ups is down? lovely
<bvernoux>
or very very slow down
<azonenberg>
carriers are still working here although i've had some shipments delayed, and some orders of canned food were canceled because amazon was unable to get them
<bvernoux>
in fact they focus to deliver only mandatory things
<azonenberg>
yes amazon is reducing their capacity for non-essentials too
<azonenberg>
focusing on food, medical supplies, etc
<bvernoux>
all company are stopped (except for food or vital things) in France and EU now
<bvernoux>
and we need to sign paper to go out to search food
<bvernoux>
military and police is everywhere to check
<Degi>
Huh yeah, I've heard that people are getting fined in france for going outsie
<azonenberg>
We're not quite at that level here, but getting close
<azonenberg>
number of cases in US is tracking Italy lagging by ~10 days
<azonenberg>
almost a perfect match to the chart
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<bvernoux>
Degi, it is confinement since 2 days now
<bvernoux>
I'm working at home ...
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<azonenberg>
There's no mandatory home confinement etc, you can still go outside as you please, but most businesses are closing down other than food and medical supplies
<azonenberg>
restaurants are still allowed to offer delivery or carry out, but no sit down dining
<bvernoux>
azonenberg, ha ok
<azonenberg>
Lots of people going outside and hiking to fight cabin fever... when you're out in the woods with nobody around you can't catch/spread germs
<bvernoux>
azonenberg, I do not know what Trump say but it is not just a flu
<Degi>
Driving tests got cancelled here today
<azonenberg>
but it beats being stuck in the house
<azonenberg>
It's a bit cold here, but if it warms up i intend to do the same
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<bvernoux>
the good things is to be far from big city when possible ...
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<azonenberg>
Yes
<azonenberg>
i've been avoiding seattle like, well, the plague
<azonenberg>
the ferries are petri dishes
<azonenberg>
out where we are there's no big crowds etc, so the only thing we have to worry about is catching something when out grocery shopping. And we're trying to make infrequent, huge orders to minimize exposure
<azonenberg>
like 3-4 weeks instead of 1-2 between food runs
<awygle>
i am out of groceries
<azonenberg>
awygle: yay
<awygle>
but i was like "oh i have a Plan! the grocery store next door is 24-hour so i'll go at like midnight"
<azonenberg>
and they closed overnight for cleaning? :p
<azonenberg>
walmart is apparently doign that
<awygle>
so i walked over there at 11:15pm last night to be greeted by a sign saying "we close at 11 now for cleaning"
<awygle>
just barely missed it lol
<azonenberg>
So show up at 10:30 tomorrow? lol
<azonenberg>
or better yet, 6am
<awygle>
yeah 10:30 today is the plan
<azonenberg>
or whenever they open
<azonenberg>
We're good for... probably another 2 weeks, but have to go out at the end of this week to refill some meds anyway
<azonenberg>
so will use that as an excuse to buy more food since we have to be out anyway
<Degi>
Today we found toilet paper...
<awygle>
ugh meds. i'm not even on anything scheduled and i still can't get more than 30 days worth of anything. what a PITA
<Degi>
Huh...
<Degi>
I hope doctors offices dont close
<azonenberg>
Degi: $wife's doc does a very quick check-in then tells you to wait in your car and they'll call you when it's time to come in
<azonenberg>
so you don't have multiple patients sitting around each other in the waiting room
<azonenberg>
they just sent out an email about the policy change
<Degi>
Hm I have backup half-used meds for 4 months tho
<azonenberg>
They aren't planning on closing since it's an essential service, just taking precautions
<awygle>
gonna run out of the meds i'm prescribed and just start taking the half-full bottles of pills i have left over from various things
<awygle>
regardless of relevance
<azonenberg>
lol :p
<awygle>
i can self-modify my diagnosis from GAD to ADHD, right?
<awygle>
dextroamphetamine-amphetamine is basically sertraline, right?
<azonenberg>
ADHD, GERD, same difference
<awygle>
my GERD drugs aren't even prescription thank god
<awygle>
and i'm stocked up for the rest of the year, thank you costco
<SingularitySurf>
Hi, sorry for rejoining a few times, didn't want my name to be cut =# Guess its full Corona here too '=D
<azonenberg>
SingularitySurf: about five of the folks in this channel live in/near seattle
<SingularitySurf>
Im 100% sure Docs etc. wont close in Germany...
<azonenberg>
so yeah
<SingularitySurf>
Full lockdown there?
<SingularitySurf>
Guess Mami Merkel is gonna announce the same here in half an hour...
<azonenberg>
Pretty close. Most/all non-essential businesses closed, gatherings over 50 people banned, people strongly encouraged to stay inside and avoid other people but not legally enforced right now
<azonenberg>
schools closed, every employer that can is working from home
<SingularitySurf>
tough... have some <3 from over here :)
<awygle>
thanks :)
<SingularitySurf>
Anyway, after the crisis I would be really interested in a fully open source, low cost USB scope with some extra features. Something like an analog discovery.
<lain>
so far I haven't had any issues with my prescriptions, they're all via PillPack though so it's all mail-deliver'd anyhow
<SingularitySurf>
And I would be interested in collaborating and putting quite some time and effort in (which I have spare anyways right now cuz my Uni is closed)
<azonenberg>
SingularitySurf: So, the design we've been working on right now is an AFE intended to be paired with a HMCAD15xx
<SingularitySurf>
Yeah exactly what I was thinking about.
<azonenberg>
Longer term plan is to build a card with four copies of the AFE, one ADC, and a samtec q-strip connector to mate it to a digital board
<azonenberg>
different people have different ideas for how the digital subsystem should be designed
<azonenberg>
degi wants a pcie card, you want a usb peripheral, and i want a self contained 1U system with ethernet backhaul
<azonenberg>
But we all have the same idea for the analog subsystem so i expect collaboration to be mostly centered around that
* awygle
also wants ethernet backhaul
<azonenberg>
I think we could make the usb and ethernet share a PCB and maybe even coexist, if 1U is OK with you?
* awygle
demands half-rack
<azonenberg>
we could even make different case options for desktop vs rackmount
<azonenberg>
awygle: so my plan is a full width 8 channel scope with two of the analog boards
<Degi>
Or maybe some adapter plate for rackmount
<azonenberg>
you can DNP one of them to cut the cost significantly and get a 4 channel
* awygle
follows azonenberg around cost-optimizing all his overbuilt designs
<azonenberg>
awygle: have you looked at the current AFE?
<Degi>
Hm I think a gigabit lan could be put on the PCIe card too. The ECP5 should have enough leftover transceivers
* awygle
has not, awygle is busy at work currently
<azonenberg>
i'm periodically pushing updates to that url
<SingularitySurf>
I aslo thik the ECP5 is an awesome platfor, FOSS toolchain and chepest bang/buck.
* awygle
is working off his extremely stressful morning by bluetext shitposting in #scopehal
<awygle>
ok i'll stop
<Degi>
Hm the version I'm targeting still costs 50 €. With least gates its like 15 € which is pretty cheap (and idk how many gates the final design takes)
<SingularitySurf>
XD
<azonenberg>
SingularitySurf: yes ecp5 is nice, i've been looking for an excuse to use it. But systemverilog is really nice and yosys doesn't work with it yet
<azonenberg>
(my whole embedded IP stack etc is all SV)
<SingularitySurf>
without SERDES they're half
<azonenberg>
so i'd need to throw away a lot of my code to be symbiflow compatible right now
<Degi>
Yes but that doesnt to PCIe
<azonenberg>
as soon as structs and enums work, we can use yosys
<Degi>
Hm can't you emulate structs and enums?
<azonenberg>
i mean you can write a converter or something
<azonenberg>
the point is more, i have thousands of lines of existing code using them
<SingularitySurf>
So Degi you want to go PCIe so you can sample directly into PC RAM?
<azonenberg>
rather than fixing the code to work on a less capable tool, i'd rather let the tool catch up
<azonenberg>
My digital board is going to be targeting a Hammond RM1U1908VBK chassis
<Degi>
Yes
<SingularitySurf>
Thats nice :D
<azonenberg>
I think these are going to end up being separate digital boards, the requirements are too different
<SingularitySurf>
Yeah
<azonenberg>
if i use an fpga with transceivers i'm going to throw 10G/40G ethernet down
<Degi>
Hm a chassis with removale mounting plate would allow converting to a desktop version
<Degi>
Yeah ECP5 only does 5G
<Degi>
(on the other hand, nmigen can compile to other FPGAs too)
<azonenberg>
yeah i'm going to stick with 7 series. The symbiflow people are actively working toward support for it
<azonenberg>
by the time that's done, i expect enums and structs to work too
<SingularitySurf>
So I am not so strongly opinioned about the final package, I just would like to help build a OS scope :)
<awygle>
this is what i meant about cost-optimizing lol
<awygle>
azonenberg: so looking at the AFE stuff, my main question is about SE vs differential
<azonenberg>
awygle: everything past the offset stage is differential, and the adc takes differential inputs
<azonenberg>
the only SE bit is the signal coming off the probe
<Degi>
Lol is that a SMA to BNC to SMA converter
<SingularitySurf>
btw sorry, I'll be back after Merkel's speech ;)
<azonenberg>
SingularitySurf: when you get back... have you looked at glscopeclient at all? played with some of the examples i've tweeted?
<awygle>
whats the bandwidth on the offset amp
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<awygle>
idk something is making me twitchy about that conversion stage
<azonenberg>
awygle: the LMH6552?
<awygle>
yeah
<azonenberg>
1.5 GHz small signal bandwidth / 1.25 GHz large signal bandwidth to -3 dB
<azonenberg>
flat +/- 0.1 dB to 450 MHz
<azonenberg>
Slightly overkill but i was going to try and reuse some of this AFE on the ~350 MHz LM97600 based scope too
<azonenberg>
and a $6.28 @ qty 1 opamp is not a huge priority for cost reduction
<azonenberg>
especially since it's $4.09 @ qty 250
<Degi>
Hm why 350 MHz on the LM9760?
<azonenberg>
Degi: Not sure on exact specs but that adc is 1.25 Gsps / 2.5 Gsps / 5 Gsps depending on interleaving
<azonenberg>
350-500 MHz is below nyquist for 1.25 Gsps so it's a convenient point for an antialiasing filter
<Degi>
Yes, I thought about 500 MHz
<azonenberg>
the 6552 can handle that
<Degi>
(though making one channel 2 GHz would be a nice addition)
<azonenberg>
then the ADL5205 should be able to do that too
<azonenberg>
i'm actually planning on building two copies of this characterization board
<azonenberg>
one with the 100 MHz filter and one with something around 500
<azonenberg>
or maybe i'll just use the other channel of the ADL5205 and double up the outputs or something
<azonenberg>
Not yet sure
<azonenberg>
The point is, i think we can reuse most of the AFE design for both scopes
<awygle>
why'd you pick a butterworth instead of a bessel-thompson?
<awygle>
... there's no p in thomson but you get the point
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<azonenberg>
Hmm, a bessel would give more linear phase response right?
<azonenberg>
Might consider doing that
<awygle>
yeah. it's a slower rolloff but you have lots of bandwidth headroom on your amp
<azonenberg>
I'm more worried about ADC aliasing actually wrt speed of rolloff
<awygle>
and hopefully a fair amount of sampling headroom on your ADC
<azonenberg>
as in 4 channel mode i'm quite close to nyquist
<azonenberg>
in fact, on 4 channel 12 bit mode nyquist is only 80 MHz
<azonenberg>
my plan is to just declare that you're on your own in 4ch 12-bit mode and to ensure your signal has little or no spectral content past 80 MHz
<awygle>
lol
<azonenberg>
maybe make that not a supported operating mode for the scope or something
<azonenberg>
say 12 bit mode is only supported on 1/2ch
<awygle>
12-bit is a bit more than is usually strictly necessary
<azonenberg>
Which prevents you from exceeding nyquist with a 100 MHz filter
<azonenberg>
The ADC can operate in 4x 250 Msps, 2x 500 Msps, 1x 1 Gsps 8-bit
<awygle>
keep in mind your butterworth isn't going to roll off _that_ fast either
<azonenberg>
as well as 4x 160 Msps, 2x 320 Msps, 1x 640 Msps 12-bit
<azonenberg>
The idea is to allow as many of those modes as possible
<azonenberg>
one option i've heard suggested is to chain two filters
<azonenberg>
you have a nice slow rolloff linear filter, then somewhere further down you have a second harder cutoff filter
<azonenberg>
which may lose some linearity but at that point you're far enough into the stopband you dont care
<Degi>
Hm can't you just stack filters?
<azonenberg>
That's what i mean. So you could have a bessel-thomson at 100 MHz and then some higher order filter at say 200
<Degi>
Like if one filter gives -20 dB/decade, adding a second one gives -40 dB/decade and using discretes you could stack like 10 filters lol
<azonenberg>
yeah that might be an option. Would need to make sure we don't add too much loss in the passband
<awygle>
yeah i'd usually say to put that after an amplifier
<awygle>
but your amplifier is negative gain
<awygle>
according to the notes
<azonenberg>
Which one?
<awygle>
the SE-to-diff offset amp
<azonenberg>
The offset stage is unity gain
<azonenberg>
When i say "net gain" i mean from probe to this point
<azonenberg>
there's a -6 dB attenuator right at the input
<awygle>
ah
<azonenberg>
prior to the offset amp
<Degi>
Hm I'd put a filter right before the ADC
<awygle>
i keep wanting there to be an AGC stage or something
<awygle>
too used to working on receivers
<azonenberg>
lol
<awygle>
that would _slightly_ defeat hte purpose
<azonenberg>
Lol. The variable gain stage is -9 to +26 dB range, which when stacked with -6 dB attenuation prior to the offset and +2 dB in the final ADC driver, gives -13 to +22
<Degi>
The ADC itself has like 30 dB
<azonenberg>
Which maximizes our usable dynamic range... -13 dB is necessary to smoosh a +/- 5V signal into the ADC's input range
<Degi>
At least for the HMCAD1511
<azonenberg>
given that constraint, +22 is the highest we can go without adding a second VGA
<azonenberg>
Which i don't think is necessary
<Degi>
Yes the HMCAD1511 has 30 dB variable gain with no missing codes
<azonenberg>
as my calculations say that with max gain we can get to ~160 mV input full scale range, which on a standard 8-div scope scale is 20 mV/div
<awygle>
you could bake your AA filter into your amplifier stage with a Sallen-Key topology lol
<Degi>
Hm yes the 1520 has digital gain too
<azonenberg>
is that no missing code gain though? or is it cheating and just stretching the output?
<azonenberg>
because i can do that myself in postprocessing on the fpga :p
<Degi>
It says no missing code to 32X :P
<lain>
yeah
<lain>
the hmcad15xx series were originally from Arctic Silicon Devices, they used to be $30 on Mouser back in 2005-era, then Hittite bought them, now Analog. they go up in price every time :P
<Degi>
And above that (to 50x) I assume that some codes go missing
<Degi>
Lol
<azonenberg>
Lol
<lain>
but the reason they're so cheap to begin with is that internally they're a really neat architecture using lots of low bit depth, fast sigma-delta ADCs iirc, and a small pile of DSP to combine them all to eliminate missing codes
<azonenberg>
anyway with no gain in the ADC i calculate 38.7 μV/LSB in 12-bit mode and 619.5 μV/LSB in 8-bit
<lain>
the architecture allows them to do funky things like adjust the response curve of individual sub-ADCs to achieve no missing code digital gain
<azonenberg>
lain: would be fun to decap one one day
<lain>
azonenberg: indeed
<lain>
as I understand it, most ADCs are still going the route of "we just need to make this one ADC faster and higher bit depth", which for >8 bits depth and >1 GS/s becomes very power hungry and uses lots of die area
<lain>
they need to get clever with it like Arctic Silicon Devices did
<lain>
:3
<azonenberg>
"smell and smoke alarms sounding, city hall evacuated"
<azonenberg>
is the hazardous conditions
<azonenberg>
Fire on 305 apparently has visible smoke from a good distance off, abandoned house fully engulfed
<monochroma>
D:
<azonenberg>
(oops wrong channel)
<Degi>
Does it make sense to lump impedance discontinuities together?
<Degi>
Like if a transmission line is terminated on both sides and has one discontinuity, then that shouldn't cause refletions in the output, right?
<azonenberg>
you'll still get stuff at the discontinuity
<lain>
the most obvious effect will be a discontinuity in the rising or falling edge, due to some of the energy reflecting back toward the source at the impedance discontinuity
<lain>
if both ends are terminated then the reflection back toward the source should not reflect off the source back toward the sink, but it will still remove energy from the signal in transit
<Degi>
Hm but if I have like a decoupling capacitor, a PCIe connector and a SMA connector, I should place the cap nearby to one of the connectors, right?
<lain>
Degi: at PCIe speeds it doesn't really matter where you place the capacitor because you can't get it "electrically close" (within a fraction of a rise time) to the source anyhow, iirc
* lain
digs up a quantitative article on the subject
<Degi>
Okay, I'll just place them somewhat nearby to the PCIe connector because other devices do that too...
<azonenberg>
ideally you want to match the impedance of the capacitor's footprint to the line
<azonenberg>
Check out xilin's UG483 around page 65
<azonenberg>
the "smt pads" section
<azonenberg>
xilinx's*
<azonenberg>
I've done a lot of modeling of this sort of thing in Sonnet, it's amazing how much of a difference it makes
<lain>
>As with any reflection, if it occurs within much less than 1/2 a baud interval of either the source or the load, the reflections generated by each data edge will generally fall somewhere within that self-same baud interval. On the other hand, reflections generated at points more remote from either source of load create interference patterns that persist into subsequent bits (i.e., intersymbol
<lain>
interference). This principle motivates the idea that DC blocking capacitors should be installed close to the transmitter.
<lain>
but yeah
<lain>
the tl;dr is to just match the capacitor impedance properly and then you won't have to worry about placement
<lain>
:D
<azonenberg>
If you have stackup and trace geometry info for me, i can go run a parameter sweep in sonnet for you to calculate the optimal cutout geometry
<Degi>
Well my traces are 0.243 mm (9.6 mils) and my components 0402, the ones in the PDF seem way smaller/bigger
<azonenberg>
and what's the prepreg thickness and dielectric material? standard fr4?
<azonenberg>
No. It can import gerbers if you buy a $$$$ addon, or DXFs
<azonenberg>
kicad export to DXF is likely the easiest import path, but with L2 Basic i can't model a super large area of a board anyway
<Degi>
I think kicad can do dxf
<azonenberg>
so not really worth it vs redrawing
<azonenberg>
once i get L3 Gold, i'll have a much larger max design size and be able to model a sizeable area of a board
<azonenberg>
At which point i'll look into importing from cad
<Degi>
Hm I mean I could just hope that this works out and if not, I'll have like 70 € lost cost unless I wanna desolder everything again...
<azonenberg>
Gimme 10 mins
<Degi>
I have a 0.264 mm width 0.15 mm gap pair going into two 0402's spaced 1 mm apart and then going into a 0.339 mm width 0.586 mm gap pair
<azonenberg>
1 oz copper?
<Degi>
0.035 mm
<Degi>
I think that's 1 Oz?
<azonenberg>
yes
<Degi>
Below that 0.2 mm of 4.6 Er dielectric and above that 0.8 mil (20 µm) solder mask with Er 3.8 (over traces 0.5 mil (12 µm))
<azonenberg>
Do you have a kicad file handy of the layout or a dxf?
<azonenberg>
if you want to model the whole transition into the split it will probably be easier to import the layout
<Degi>
Hm only of the whole thing
<Degi>
But yes I could make a layout
<azonenberg>
send me whatever region you want, i can trim out unrelated geometry
<Degi>
How do I best send files?
<azonenberg>
(my nick) at drawersteak.com is good
<Degi>
In mm or inches?
<azonenberg>
mm
<awygle>
speaking of sonnet, did you ever get results from those PCIe GCPW sims you did?
<azonenberg>
awygle: i seem to recall you saying you didn't need them after all, so i never finished
<awygle>
ah ok
<awygle>
i mean i never _needed_ them
<awygle>
i was just curious if the sim matched my calculations
<awygle>
nbd tho
<Degi>
Sent you
<azonenberg>
Got it imported, let me crop out the fun bits
<Degi>
Hm I changed that board a bit now, that all cap pairs on the PCIe section get the signals straight on (before that, the refclk pair on the left had a bend) because I noticed that I didn't really pay attention to the mechanical spec lol
<Degi>
Hm crap the PCB will cost like 60 bucks
<azonenberg>
you realize the hmcad1520 is like $100 just for the adc right?
<Degi>
Yes
<Degi>
But this is the ECP5 EVN to PCIe adapter board PCB (and the first ever PCB I'll get manufactured instead of etching it myself)
<azonenberg>
Are you going to have ground planes under the PCIe edge connector, or not?
<Degi>
No
<Degi>
Ground planes start when the PCIe pins end
<azonenberg>
OK
<azonenberg>
and the two pins on either side of the diffpairs are ground?
<Degi>
Like if I wanted 100 pcs its like 1.85 € per PCB but if I want one, the MOQ is 5 anyways, I pay 60 $ (ENIG 14.5 $, Stencil 7 $, Board 6.9 $, 32 $ engineering fee)
<Degi>
Yes
<Degi>
Well not all of them, but assume ground should be close enough
<Degi>
Tbh I think the SMA connectors will overshadow any distortion from the capacitors anywys.
<azonenberg>
ok so initial model wants to use 288 MB of ram, the limit for my version is 128. Let's see how much i can simplify this...
<azonenberg>
If i turn the meshing down to coarse from fine, it's only 41 MB
<Degi>
Oof
<Degi>
Hm could OpenFOAM be used for this kind of stuff?
<azonenberg>
The limit for L2 Silver is 256, and L3 Gold is 2048
<azonenberg>
It seems mostly meant for CFD. OpenEMS's solver has a lot of potential but there's ~no UI right now
<azonenberg>
Which makes it pretty useless
<azonenberg>
oops i forgot to add the coupling caps :P that would explain the weird results i got lol
<azonenberg>
oh wait i need to make the vias extend a bit past the ground pins so they hit the ground plane
<Degi>
Hm that looks pretty nice
<Degi>
Tbh FOSS projects generally seem to be lacking a GUI when its not absolutely necessary...
<azonenberg>
Yeah. But something like this it *is* necessary
<Degi>
Sometimes it lacks even if it is necessary lol
<azonenberg>
imagine a PCB layout tool where you have to write python scripts to draw all of your geometry and then use third-party tools to look at the generated gerbers
<azonenberg>
That's literally the level of maturity openems is at now
<azonenberg>
it's a nice solver that's completely unusable because of the total lack of any kind of ui
* awygle
coughs, gestures at pcbhdl
<azonenberg>
HDL for netlist entry makes sense, as netlists are not inherently graphical/physical in nature
<azonenberg>
*layout* on the other hand is
<awygle>
:p
<Degi>
Hm is there a verilog to gerber compiler yet
<Degi>
Maybe nextpnr can do PCBs
<azonenberg>
The amount of constraint work involved in making a FULL autorouter including placement of components etc would be a major moonshot level project
<Degi>
Do such things exist yet?
<azonenberg>
Not to my knowledge
<Degi>
I mean microchip designs are made somehow automatically
<azonenberg>
ASIC and PCB layout are quite different problems
<azonenberg>
ASICs generally assume you've got a LOT of metal layers, PCBs tend to be relatively few
<Degi>
Hm
<azonenberg>
i think 28nm TSMC has something like 11-12 metal layers by default?
<azonenberg>
typically you have one right over the transistors to interconnect them into gates, then alternating H/V
<azonenberg>
all of your vias are blind/buried and generally the same diameter as your traces
<azonenberg>
all of your gates are standardized heights and mutliples of standard widths
<azonenberg>
laid out in neat rows
<azonenberg>
and you still typically have a human guide the top level floorplan
<azonenberg>
I think the more viable option near term is synthesizing HDL to a netlist you then lay out mostly by hand
<sorear>
when manual routing is full-stop impossible, people accept higher levels of inefficiency
<azonenberg>
rather than schematic entry
<azonenberg>
And yes, that
<Degi>
Hm yes, that sounds kinda simpler than hundreds of different components
<azonenberg>
it's a huge instance of a simpler problem
<azonenberg>
(millions of gates or more)
<azonenberg>
ok hmmm, simulation finished... rather interesting
<azonenberg>
it's showing almost 100% of the signal reflected and i'm trying to figure out why
<azonenberg>
S21 is about -55 dB at best :p
<azonenberg>
wonder if one of my ports isn't making contact with something etc
<azonenberg>
oh, derp
<azonenberg>
typoed one of the port numbers
<Degi>
Welp
<azonenberg>
also having a weird issue with the capacitors that i don't fully understand. Temporarily going to replace them with jumpers. Shouldn't change the matching at RF much
<azonenberg>
ok so with your layout as is, the sim is showing a massive reflection (nearly -5 dB return loss) from about 2-6 GHz
<azonenberg>
at about 1.5 GHz it drops below -10, there's a dip down to -15 around 8 GHz, then it rises again
<Degi>
Hm how much is transmitted?
<Degi>
Can you send a picture of the current setup?
<Degi>
I mean as long as the transmission loss is like only 2-3 dB or so that should be fine
<Degi>
(Like total budget for a 2.5 Gbit link is 13.2 dB at 1.25 GHz
<azonenberg>
I think i can make it much better, this is just a start
<Degi>
Is blue the transmission?
<azonenberg>
Blue is S21, yes.
<azonenberg>
red is reflected
<azonenberg>
That's pretty awful. Definitely possible to make it better
<Degi>
Idk that looks pretty ok for me
<Degi>
As far as I know, the transceivers are terminated
<Degi>
Is that the return loss from the PCIe side or from the other side? Because the signal will be incoming from the other side
<azonenberg>
That's S11 which is reflection off port 1 (left side)
<azonenberg>
pcie is port 2
<azonenberg>
S22 is actually slightly less bad
<Degi>
Ah now I think I understand S values
<Degi>
Yes S11 is what I care about and -5 dB is well... I guess that is within spec
<azonenberg>
well this was the initial sim before any optimization :)
<Degi>
Optimization of the design? Or of the sim?
<azonenberg>
give me a minute. Now rerunning with a somewhat arbitrarily sized cutout under the 0402s. If that produces a noticeable result, I'll do a parameter sweep for x/y cutout size
<azonenberg>
and let you know what worked best
<Degi>
I mean the thing is the differential pair to SMA to differential pair transitions probably have some rather high return loss as well
<azonenberg>
yes, so you probably want this part to be well matched to get as good as you can
<azonenberg>
(personally i would have used edge launch SMAs...)
<Degi>
Hm not really possible, this board screws right on top of the dev board (because SMA cable pricy)
<Degi>
In the final design, there will be no SMAs and the caps will be directly on the ECP5 (<< 1 bit size)
<azonenberg>
Well this is interesting. Adding the cutout greatly improved return loss at ~9 GHz
<azonenberg>
But i don't see a huge improvement in the lower freqs. Wonder if it's the PCIe transition that's reflecting
<Degi>
I think the frequencies I'm interested in is 1.25 GHz, 2.5 GHz, 3.75 GHz, 7.5 GHz
<Degi>
I think the whole PCIe connector is kinda meh
<Degi>
I think I mostly care about transmission loss. It looks kinda worse now...
<zigggggy>
im back from shoprite azonenberg
<Degi>
Specifically S11 at 2.5 GHz
<Degi>
No, S21
<monochroma>
zigggggy: did you survive?
<Degi>
Thanks for the simulations
<zigggggy>
it was actually not bad at all
<zigggggy>
went at 3:30 pm
<azonenberg>
yeah it's worse in that range. But i'm more interested in the fact that it improved higher speed reflections. Now modeling (added to that cutout) mitering at the pcie connector
<azonenberg>
vs a step width change
<zigggggy>
maybe busier than usual, but i had no trouble getting in and out
<zigggggy>
i think going before 5pm is key
<zigggggy>
and after lunch too
<zigggggy>
morning has a lot of panickers i hear.. after 5pm are people after work
<Degi>
Huh done with bottom layer differential pairs
<azonenberg>
Ok this seems to be helping
<azonenberg>
Let me move S21 to the other axis so it's scaled better
<azonenberg>
so S21 is now zoomed in more and you can see the dips more clearly, they pretty much exactly match up with the reflections which makes sense - there's not a lot of resistive/dielectric loss
<azonenberg>
Return loss is below -5 dB for the whole range now. So this is an improvement
<azonenberg>
this is with no cutout under the resistor but mitering and a cutout at the PCIe connector
<azonenberg>
next step will be to run a sweep to optimize the cutout sizes there
<Degi>
Hm I mean under the whole PCIe is no copper. 1.6 mm below the top copper is the bottom copper of the PCIe (which I guess can be assumed ground? Though there's differential signals there too)
<azonenberg>
Yeah i'm talking about as you transition from the narrow line to the fat one
<azonenberg>
you don't want a sudden change, you want an angled edge
<azonenberg>
This will take a while as it's running through 7 different combinations, i'll show you the results when it's done
<azonenberg>
slowly necking down, with a ground cutout at the transition
<Degi>
Huh neat
<azonenberg>
The idea is to open up the ground as the trace gets wider so, as the geometry changes, each slice has uniform impedance
<azonenberg>
and you don't actually get a mismatch
<Degi>
I'm not sure how many fucks were given about impedance when designing the PCIe connector tbh.
<Degi>
A copper plane 1.6 mm under the PCIe pins may improve performance (at least it exists IRL in the form of ground pins)
<azonenberg>
Right now i'm modeling the grounding as all being relative to the adjacent pins
<Degi>
Are thermal vias under QFNs fine or do they suck up too much solder?
<azonenberg>
I haven't had problems with them, just use the smallest drills your fab lets you within reason
<azonenberg>
unfilled via in pad under a BGA or small passive pad is an absolute no-no
<azonenberg>
on a giant thing like a d2pak or qfn thermal slug, a little voiding isn't gonna make an open circuit or significantly hurt the joint
<Degi>
Yes 0.2 mm, guess that's fine
<Degi>
Hm would it be possible to fill pads under BGA with solder before soldering?
<azonenberg>
I have not seen a viable "poor man's via-in-pad" technique yet
<azonenberg>
which is why for cheap stuff i try to stick to 1mm packages as those are easy to do with dogboned vias
<azonenberg>
anyway it looks like your big mismatch is at the pcie connector so try to miter it
<azonenberg>
Cutout there doesnt seem to be having a huge effect
<Degi>
Hm is it bad to have a cut ground plane with a trace inbetween under a diff pair?
<lain>
Degi: extremely
<Degi>
Even when I have 2 ground planes and place a lot of vias from the first to the second around the cut? Also the cut would be90° to the diff pairs
<lain>
current flows in a loop. the current through the trace has a corresponding return current in the coupled plane, and that return current will be directly underneath the trace
<lain>
if the plane is not continuous under the trace, that return current will have to flow around the cut
<Degi>
Isn't the return current within the differential pair?
<lain>
the coupling between the trace and the return current determines the impedance
<Degi>
(though they are terminated to ground yes)
<lain>
Degi: on pcbs, diffpairs have almost no coupling between the P/N sides, it's almost 100% to the reference plane
<Degi>
Hm
<lain>
also note that the coupled plane does not have to be ground, any plane will do, it should just be continuous
<Degi>
Well I just need to get a signal from one side to the other and both sides of the PCB have differential pairs. Guess I could just route around them
<lain>
also when changing layers, you need to be sure either: a/ the traces reference the same plane on either side, or b/ the planes are connected with stitching vias (if same potential) or decoupled together with caps (if different potential) near the signal vias
<Degi>
Okay. For now the diff pairs all stay on one layer
<lain>
for example if your stackup has signal on top and bottom, with layer 2 GND and layer 3 +3v3, if a high speed trace moves from top to bottom, it necessarily changes from referencing GND to referencing the +3v3 plane, so decoupling caps must be placed between GND and +3v3 planes as close as possible to where the signal changes layers
<lain>
the decoupling capacitor acts as an AC path for the return current
<Degi>
Hm yes
<lain>
the way I tend to visualize it is: if the return current ever has to stray away from its corresponding trace, the E-field coupling the trace to its reference plane will have to go further. this has two implications: 1/ larger loop area means larger cross-section for generating and receiving interference (it's an antenna), 2/ this implies an impedance change (same as if the reference plane were further away
<lain>
in general, for the distance around the plane cutout)
<Degi>
Hm is it possible to taper a trace in kicad? Or do I need a pad for that
<lain>
also crosstalk -- if you have for example two traces that cross a cutout/slot in a plane, both their return currents will hug the cutout, trying to stay close to their traces. this implies their return current will bunch up as they both go around the cutout, which will cause some crosstalk
<Degi>
How does PCIe2.0 not shit all over the wifi band?
<azonenberg>
usb 3.0 does, right? :p
<Degi>
Yes
<Degi>
PCIe2.0 has the same data rate
<miek>
and hdmi, sometimes... :)
<lain>
Degi: yeah, the issue is typical trace geometry is such that, if a reference plane exists and is even remotely close, it'll couple much stronger to that than to the other half of the diffpair, so the impedance is primarily determined by the reference plane
<lain>
and yeah I think the main reason pcie doesn't shit all over wifi is FCC/CE testing :P
<lain>
which is to say, it does, but manufacturers are forced to try their best to make it not
<Degi>
Are thermal reliefs on SMA connector ground pins okay? (Through board connector with 5 holes, not edge launch)