<lkcl>
for anyone looking to do pre- and post- layout synthesis of a design, to make sure it's not "damaged" by the P&R, i'm currently getting that up and running, here https://git.libre-soc.org/?p=soc-cxxrtl-sim.git;a=tree;
<lkcl>
it's using whitequark's new cxxrtl yosys plugin
<lkcl>
importing the cell library VHDL files (using the yosys ghdl plugin)
<lkcl>
phases 1 and 2 are complete, phase 3 - extracting the netlist after coriolis2 has finished P&R - is TBD
<lkcl>
all three phases use the exact same JTAG "programmer" and can also use openocd with .svf files, with the jtagremote "bitbang" interface
mkk_ has left #skywater-pdk [#skywater-pdk]
mkk_ has joined #skywater-pdk
<mkk_>
[Jason Kridner, skywater-pdk] hi @Drew Fustini and @mkk.
<mkk_>
[Drew Fustini, skywater-pdk] Hi!
<mkk_>
[John Hribar, skywater-pdk] Hey everybody! I decided to join after watching the SSCS presentation. Really excited to be here!
<mkk_>
[Hunter Futo, skywater-pdk] Hi all! I joined from OSHWA. I've been inching more into the wearables (medical, biosensing) space lately, looking forward to edge, and concerned about security. Not ready to dive into ASIC design quite yet but I am going to watch and lurk until I can carve out the time to learn.