05:00 <mkk_> [Kunal Ghosh, skywater-pdk] @Channel Now that's what you can achieve in a 5-day VSD workshop, in contrary to other workshops happening all over the world - *Your own design, your own RISC-V basic core and complete control over your core*. Not only that, the RISC-V core coming out of this workshop is COMPLETELY SYNTHESIZABLE. What does it mean? You can burn your RISC-V core either on *FPGA* on 6th day itself and test it OR you can t

05:00 <mkk_> https://www.vlsisystemdesign.com/what-i-did-in-5-day-vsd-workshop-designed-basic-risc-v-core/

08:41 <mkk_> [Farhad Modaresi, skywater-pdk] Hello,

08:41 <mkk_> When would the efabless mpw shuttle program submissions be open again?

18:22 <lkcl_> P&R successfully completed on the 180nm Libre-SOC ASIC using coriolis2 from Sorbonne University https://libre-soc.org/180nm_Oct2020/2021-03-09-ls180.png

18:23 <lkcl_> this includes 4x 4k SRAM Cells kindly custom-developed by Staf Verhaegen for us, of Chips4Makers

18:24 <lkcl_> the 4k SRAM cells are around 0.7 mm^2 so you can get an idea of the overall size from that.

23:16 <mkk_> [Rob Taylor, skywater-pdk] lkcl: are you measuring coverage?