18:33 <mkk_> [Michael Heidinger, skywater-pdk] A question from the economic side: what costs 1mm2 chip area in sky130 for say 100k chips? Or the other way: What does a processed wafer cost? What are the setup costs? What are packaging cost? What are test cost? Is there a business spreadsheet for this?

21:21 <mkk_> [Staf Verhaegen, skywater-pdk] @ This chip will be pad limited as we fill up half a MPW block with maximum number of IOs in the ring. But Coriolis can typically do routing in 0.18µm with only 5 or 10% area overhead. The standard library is not area efficient yet though; I think something like 16-18 track height.