<mkk_> [Wenbo Duan, skywater-pdk] Hi everyone! @mehdi and I have been working on OpenFASOC a fully open source analog block generation based on FASOC (https://github.com/idea-fasoc/fasoc) using fully open-source tools like OpenROAD, Magic and Netgen. So far, we have pushed an automated temperature sensor generator to github: https://github.com/idea-fasoc/OpenFASOC. Please have a look and try our generator and let us know if there are any
<mkk_> [Tim 'mithro' Ansell, skywater-pdk] Everyone should be like Anton -> https://twitter.com/antonblanchard/status/1372073503898226688 !
<mkk_> [Tim 'mithro' Ansell, skywater-pdk] https://twitter.com/OlofKindgren/status/1374848733746192394
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<mkk_> [Klas Nordmark, skywater-pdk] Speaking of Edalize, we're getting around to work on Openlane support now. Just doing preliminary work at the moment, putting SERV through the flow (our intended example), checking how Caravel does things...
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<mkk_> [Klas Nordmark, skywater-pdk] Yep, since quite recently. We've managed to scrounge up some money to work on this, me on full-time potentially for the next two months. I'd expect to continue helping out with the Fusesoc project afterwards as well.
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<mkk_> [Tim 'mithro' Ansell, skywater-pdk] @Klas Nordmark Cool! You should also talk to Anton
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<mkk_> [Tim 'mithro' Ansell, skywater-pdk] https://github.com/ieee-ceda-datc/datc-rdf-calibrations#datc-rdf-calibrations looks super interesting
<mkk_> [Tim 'mithro' Ansell, skywater-pdk] @Klas Nordmark You should reach out to Anton and see if he is willing to be a guinea pig with MicroWatt too
<mkk_> [Tim 'mithro' Ansell, skywater-pdk] @Klas Nordmark Yeap!
<mkk_> [Tim 'mithro' Ansell, skywater-pdk] @Klas Nordmark I believe he is in the Australian timezone, so probably not around right now
<mkk_> [Tim 'mithro' Ansell, skywater-pdk] People have seen https://antmicro.com/blog/2020/04/systemverilog-linter-and-formatter-in-fusesoc/ right?
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