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<mkk_>
[Dan Ravensloft, skywater-pdk] I've been looking at automatic generation of standard cell libraries. Even if the cells generated are 20% worse than hand placement, I'm reasonably confident that the resulting netlist will still end up smaller due to gate fusion.
<mkk_>
[Dan Ravensloft, skywater-pdk] Similar to how it's more efficient to build an AOI21 gate out of 6 transistors compared to the 10 that it takes to build it out of separate gates.
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<mkk_>
[Rob Taylor, skywater-pdk] @Lofty interesting - found any good relevant papers?
<mkk_>
[Kunal Ghosh, skywater-pdk] What if I told you that in 5-days, you can learn a new hardware description language and build your own basic RISC-V core? You won't believe me, right? One of the first few, infact only 2 or 3 companies in whole world including VSD have *adopted to cutting edge technology like TL-Verilog, RISC-V and VSD-IAT system for efficient online learning*
<mkk_>
[Tim 'mithro' Ansell, skywater-pdk] CircuitVerse is a product developed by students at IIIT-Bangalore.
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<mkk_>
[Dan Ravensloft, skywater-pdk] Okay, so, I wrote a quick proof of concept Liberty library generator based on BDDs. It only goes up to 4-input gates, but it's something
<mkk_>
[Dan Ravensloft, skywater-pdk] It's effectively just transistor networks at the moment, but it's something