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Title: Manually set inputs as clock SymbiFlow Verilog to XML (V2X) 0.0-514-ge4b87e3 documentation (at python-symbiflow-v2x--74.org.readthedocs.build)
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Title: read_place: do not throw error if block name is invalid by acomodi · Pull Request #1541 · verilog-to-routing/vtr-verilog-to-routing · GitHub (at github.com)
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<acomodi> @mithro: some of the tests in symbiflow (carry-stress) are autogenerated (both design, and constraints file) based on tests parameters defined in CMake, and all the tests are generated for each board/device.
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<acomodi> mithro: After synthesys, some of the tests for ice40 do not have all the IO signals connected, therefore VPR produces a packed netlist without the unconnected IO signals.
<mithro>
@acomodi: Can you be more specific about what is unconnrected?
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<acomodi> In the paste there, there is the design, the output eblif and the PCF. The carry_fabric signal is the unconnected signal in this case, which is present in the PCF
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<acomodi> I believe that another solution would be to add a fix to the IO placement script that generates the placement constraints for VPR, so that it avoids outputting the constraint itself, if the related signal is unconnected. I need to check if this is easily doable
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