08:04 <sf-slack> <olof.kindgren> @lofty. It does, but I don't think there's anything in it that maps well to a 2-bit wide memory. And implementing it as logic is too large. Will need to massage the memory interface a bit to make it 8-bit instead

08:04 <sf-slack> <olof.kindgren> Think it should be parameterizabe already come to think of it...

08:12 <sf-slack> <olof.kindgren> Will have to give it a try later today

10:06 <aep> hi, is there a getting started doc for ecp5?

10:07 <daveshah> https://github.com/ulx3s/quick-start has some good pointers

10:07 <tpb> Title: GitHub - ulx3s/quick-start: ULX3S Quick Start (at github.com)

10:09 <aep> thanks. might be useful. (i have a versa 5g tho)

12:37 <sf-slack> <olof.kindgren> @aep There's no support yet for the Versa board in project LED to Believe. That could be a good starting task

12:37 <sf-slack> <olof.kindgren> https://github.com/fusesoc/blinky

12:37 <tpb> Title: GitHub - fusesoc/blinky: Example LED blinking project for your FPGA dev board of choice (at github.com)

12:39 <aep> sf-slack: hah, thats a great idea

13:09 <sf-slack> <olof.kindgren> And from there it's just a tiny tiny step to be running the world's smallest RISC-V CPU. :)

13:11 <sf-slack> <olof.kindgren> And after that it's just a tiny tiny step to run dozens of RISC-V CPUs on the board at once

13:13 <Lofty> olof: Do you have a corescore for the Cyclone 10 GX?

15:30 <sf-slack> <olof.kindgren> Not yet

15:31 <sf-slack> <olof.kindgren> But just extrapolating from the stratix v results I reckon it could fit 24000 cores. But that number could be wildly off

15:32 <sf-slack> <olof.kindgren> For the GX 10M I mean

15:41 <Lofty> I have like a 220K ALM board, so

15:45 <sf-slack> <olof.kindgren> Interesting. Should we find out? :)

16:09 <Lofty> When I get home in a few days, sure

16:39 <sf-slack> <olof.kindgren> Awesome. Just ping me if you need any assistance

19:21 <sf-slack> <olof.kindgren> Aha. Seems like the BRAM pass in yosys thinks it's to inefficient to implement as memory, so it rejects it

19:22 <sf-slack> <olof.kindgren> Any way to set the `min efficiency`? Can I do it with a TCL command, or is it hard coded in the source? Can I use a verilog attribute to make it use a RAM?

19:22 <sf-slack> <kgugala> @olof.kindgren is this project available anywhere so we can play with it

19:22 <sf-slack> <kgugala> Or maybe a minimal RAM example

19:23 <sf-slack> <olof.kindgren> It's SERV

19:23 <sf-slack> <olof.kindgren> But the quickfeather target isn't available yet

19:24 <sf-slack> <olof.kindgren> This is the file https://github.com/olofk/serv/blob/master/rtl/serv_rf_ram.v

19:24 <tpb> Title: serv/serv_rf_ram.v at master · olofk/serv · GitHub (at github.com)

19:27 <sf-slack> <olof.kindgren> The particular configuration I look at uses width=8, csr_regs=4 which gives depth=144 and a total number of used bits will be 1152

19:27 <sf-slack> <olof.kindgren> Yosys has this to say ``` Checking rule #2 for bram type $__QUICKLOGIC_RAMB8K (variant 1): Bram geometry: abits=10 dbits=8 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__QUICKLOGIC_RAMB8K: awaste=880 dwaste=0 bwaste=7040 waste=7040 efficiency=14 Rule #2 for bram type $__QUICKLOGIC_RAMB8K (variant 1) rejected: requirement 'min efficiency 50' not met.```

19:27 <sf-slack> <olof.kindgren> efficiency=14 comes from 1152/8192

19:28 <sf-slack> <olof.kindgren> Personally, I'd say that's a bit too much to require 4096 bits to be used

19:28 <sf-slack> <olof.kindgren> Since it's a small FPGA I'd reckon perhaps 64 or 128

19:29 <sf-slack> <olof.kindgren> But I have no idea what the usual trade-off is here

19:31 <sf-slack> <olof.kindgren> Looking now at a yosys log from the ice40 backend where it seems to accept 7% efficiency

19:31 <sf-slack> <kgugala> so the mapping rules are defined here https://github.com/QuickLogic-Corp/yosys/blob/quicklogic-rebased/techlibs/quicklogic/pp3_brams.txt

19:31 <tpb> Title: yosys/pp3_brams.txt at quicklogic-rebased · QuickLogic-Corp/yosys · GitHub (at github.com)

19:31 <sf-slack> <kgugala> and efficiency there is set to 50

19:32 <sf-slack> <kgugala> you can try play with it

19:32 <sf-slack> <olof.kindgren> Got it. Is this compiled, or can I just change this file in my installation?

19:32 <sf-slack> <kgugala> yep

19:32 <sf-slack> <kgugala> the script uses external txt file https://github.com/QuickLogic-Corp/yosys/blob/quicklogic-rebased/techlibs/quicklogic/synth_quicklogic.cc#L170

19:32 <tpb> Title: yosys/synth_quicklogic.cc at quicklogic-rebased · QuickLogic-Corp/yosys · GitHub (at github.com)

19:45 <Lofty> kgugala: I'd strongly recommend turning efficiency way down. 5% is probably sufficient

19:46 <Lofty> IIRC QuickLogic don't have LUTRAM

19:46 <Lofty> Which means, like a 4095-bit memory is going to be turned to flops

19:47 <sf-slack> <olof.kindgren> https://github.com/QuickLogic-Corp/yosys/pull/34

19:47 <tpb> Title: Allow less efficient use of BRAM resources by olofk · Pull Request #34 · QuickLogic-Corp/yosys · GitHub (at github.com)

19:47 <sf-slack> <olof.kindgren> And the servant SoC now fits in the quickfeather :)

19:48 <sf-slack> <olof.kindgren> That's it for tonight

19:48 <sf-slack> <kgugala> yeeey

19:49 <sf-slack> <kgugala> @lofty turning it down makes perfect sense, thanks for the tip

19:52 <Lofty> How's ABC9 going?

20:17 <arturswiderski82> quit