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<umarcor> Hi! I was wondering what is the format used in Yosys -> Quartus workflows.
<umarcor> I saw Quartus -> VQM -> vqm2blif -> BLIF -> VPR.
<umarcor> Is Yosys -> ??? -> Quartus supported?
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<Lofty> umarcor: hi, I'm the developer of the Yosys frontend for Intel chips
<Lofty> Yosys can output directly to VQM for Quartus
<Lofty> This is in fact mainly how I use it
<umarcor> Lofty: hi! so, is VQM used either as an input from open source tools to Quartus os as an output from Quartus to open source tools?
<Lofty> The former
<umarcor> No JSON, EDIF, BLIF or other formats are used/supported by Quartus?
<Lofty> Fundamentally though it's a Verilog netlist of cells
<Lofty> EDIF is apparently supported, but EDIF is a horrendous format
<umarcor> Note that I'm asking this because I'm drawing a diagram of the ecosystem.
<Lofty> Output to nextpnr would use JSON
<umarcor> I don't have any strong interest on one format or the other, but just understanding what the current state is.
<Lofty> And I presently have no intentions of using VPR.
<umarcor> How do you get from VQM to a bitstream for Intel devices?
<Lofty> Well, Yosys takes in the Verilog and produces a .vqm file
<umarcor> Is it Yosys -> VQM -> Quartus -> Bitstream?
<Lofty> Yes
<umarcor> Thanks!
<umarcor> Out of curiosity, did you try VHDL or are you a Verilog only user?
<Lofty> VHDL input for Yosys would use the GHDL plugin
<Lofty> Which seems to work okay
<umarcor> Indeedd... I'm an active contributor to GHDL.
<umarcor> I take care of the docs, CI, etc.
<umarcor> That's how I approached Yosys and Symbiflow.
<Lofty> I wouldn't really call the Intel flow part of Symbiflow any more than I would call the ECP5 flow part of Symbiflow
<Lofty> But that's neither here nor there
<Lofty> 'the Intel flow' is codenamed Project Mistral, FWIW
<umarcor> However, Quartus -> VQM -> BLIF -> VPR is a documented flow. Does that fit into Symbiflow?
<umarcor> Is this the official repo of Project Mistral? https://github.com/Ravenslofty/mistral
<Lofty> umarcor: that flow seems like the worst of both worlds
<Lofty> Especially when you consider that Quartus uses a heavily modified VPR internally anyway
<Lofty> [09:42:54] umarcor: Is this the official repo of Project Mistral? https://github.com/Ravenslofty/mistral <--- 'kinda'
<umarcor> In fact, I feel that Yosys -> BLIF -> VPR makes more sense than using Quartus. Nonetheless, I'm trying to document what's possible, to then discuss what's sensible.
<Lofty> Well, since Yosys doesn't output Intel netlists to BLIF that's distinctly *not* possible
<umarcor> Is it not possible or not implemented?
<Lofty> "I won't support it"
<umarcor> Oh, that's ok. I'm not implying any of the commented workflows needs to be actively supported.
<Lofty> The chips I'm focusing on are the Cyclone V and Cyclone 10 GX.
<Lofty> VPR does not have models of those, to my knowledge
<Lofty> So while adding BLIF output is a one-liner, I'm not writing the VPR models for the hardware
<umarcor> VPR is transitioning very fast from dealing with theoretical models to supporting Xilinx devices. Hence, it is possible that Intel devices are supported in VPR in the not far future.
<umarcor> Anyway, thanks a lot for the insight about what's possible at now, and what are your expectations.
<umarcor> much appreciated
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<sf-slack> <pgielda> Well, VPR already supports Xilinx and Quicklogic devices, so the transition happened. But its important for the health of Open Source ecosystem that multiple tools are supported and are interoperable.
<sf-slack> <pgielda> (unlike "vendor" tools that are usually not)
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<umarcor> pgielda: is VPR the only supported toolchain for Quicklogic devices?
<sf-slack> <kgugala> @umacor: VPR is the only opensource toolchain for QL devices
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<umarcor> kgugala: do you mean that https://www.quicklogic.com/software/legacy-fpga-tools/ exists?
<tpb> Title: QuickLogic Legcy FPGA Tools | QuickLogic Corporation (at www.quicklogic.com)
<umarcor> or is there a non-legacy non-opensource alternative?
<sf-slack> <kgugala> QL switched fully to open source
<sf-slack> <kgugala> the legacy proprietary tool sare available on the website you linked
<umarcor> thanks!
<_whitenotifier-f> [symbiflow-tools-package-manager] kgugala opened issue #3: Add format checker to CI - https://git.io/JTX7Q
<_whitenotifier-f> [symbiflow-tools-package-manager] kgugala opened issue #4: Add License checker to CI - https://git.io/JTX75
<_whitenotifier-f> [symbiflow-tools-package-manager] kgugala opened issue #5: Update README - https://git.io/JTX5C
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