clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
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<ZipCPU> Hi, tito_! Did you read through those tutorials?
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<tito_> hi
<ZipCPU> Hi, tito_! Did you read through those tutorials?
<tito_> you are still tying zbasic on zipcpu ....... and also Verilator, but I'm still stationary ........... I have installed CYGWIN but I can not use it .......... ..
<ZipCPU> Really? Why not?
<ZipCPU> What's the problem?
<tito_> he i use windows and if i can i use powershall ........... ga what i know i have to start make :(
<ZipCPU> Did you see my blog post regarding installing cygwin? It doesn't require or use powershell ...
<tito_> link to please
<tpb> Title: Windows FPGA designers may not need a Linux machine ... yet (at zipcpu.com)
<ZipCPU> I have to be careful that those instructions don't get out of date, so please let me know if you run into problems.
<tito_> I read, thanks
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<bog_dan_ro> hello, does yosys support xilinx CPLDs (XC9572XL)?
<daveshah> bog_dan_ro: As I understand it, Yosys can do basic synthesis and mapping using ABC for sum-of-product architectures, but does not support many more advanced CPLD features
<daveshah> There is no bitstream generation support for that CPLD, but rqou is working on that (and PAR support and Yosys improvements) for the CoolRunner-II
<bog_dan_ro> daveshah: thanks a lot, i"ll keep an eye on github ;-)
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