<dmin7>
hmm .. so it seems like icosoc and also picosoc can't actually address the spi flash after initialization (on the icezero).
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<dmin7>
is there any icosoc / picosoc examples out there that have the spi flash directly attached to the ice40 and external pi/micro that i might have missed?
<dmin7>
i found the micropython port
<dmin7>
the black ice ii (icosoc) .. but that just removes all of the spi flash components
<dmin7>
tinyfpga .. but it doesn't seem like he pushed any changes to the picosoc fork
<dmin7>
the micropython port would be interesting, but it gives me a "micropython.blif:10708: fatal error: unknown formal `CLKHFEN[0]'" after changing the chip and package name and .pcf assignments to the 4K
<daveshah>
dmin7: there is no internal oscillator in the 4k
<daveshah>
you will have to modify it use an external clock input
<ZipCPU>
daveshah: You've done a lot of work with the picosoc, right? Have you ever tried to set up the flash to start immediately on power up?
<daveshah>
ZipCPU: I've only ever used "plain" picosoc, which is always configured like that
<daveshah>
I've never used icosoc
<daveshah>
The micropython example for example just boots straight from flash
<daveshah>
dmin7: you can't use clk directly and through a PLL40_PAD at the same time
<daveshah>
it's a terrible error message I know
<daveshah>
you can remove the reset counter, and just connect resetn to locked
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<mazzoo>
playing on picosoc; why can't I insert the PLL as main clock? icetime says 30MHz is possible, but even with 12MHz (==input xtal) the runtime stalls
<daveshah>
mazzoo: What board are you using?
<daveshah>
Several popular boards have broken VccPLL wiring
<mazzoo>
axelsys breakout board
<mazzoo>
pll works fine for standalone a 135MHz VGA sig gen
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<mazzoo>
upscaling from the 12M xtal
<daveshah>
mazzoo: should be OK then
<daveshah>
Can you post your complete design somewhere?
<daveshah>
Do you have resetn driven by pll locked?
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<mazzoo>
daveshah: oh, i ignore pll lock, but there's a resetn counter
<daveshah>
Try connecting resetn to locked
<mazzoo>
thx
<daveshah>
The clock output may otherwise be unstable for a bit and cause problems by corrupting state
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<mazzoo>
works perfect.
<mazzoo>
<3
<mazzoo>
thanks again!
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<daveshah>
mazzoo: awesome!
<develonepi3>
Hello Pin C8 is my USER_CLK comes from a 100MHz osc. It is connected to IOT_197_GBIN1 on HX8K.
<develonepi3>
When I try using it for as an input to PLL I get the fatal error: bad constraint on `i_clk': no PLL at pin C8.
<develonepi3>
Can only certain pins be used as inputs to PLL?
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<daveshah>
develonepi3: use the SB_PLL40_CORE instead of SB_PLL40_PAD variant (and REFERENCECLK in instead of PACKAGEPIN)
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<thoughtpolice>
I have a bit of an odd question, perhaps. I'm basically just trying to get some cell numbers on a large design when mapped to an ASIC gate library (.lib) -- but one issue is that when I do synthesis, all of my RAMs in the original design are mapped to DFFs, which clearly skews the metric; in reality these would be SRAMs or whatever. Does anyone know of a good way to ignore memory->DFF conversion for some part of the hierarchy?
<daveshah>
thoughtpolice: its just a case of not running the "memory" pass on those parts to leave the memory as a black box I think
<daveshah>
But I'm not sure of the details
<thoughtpolice>
Yeah, I just realized I stupidly had a 'memory' hanging out in my script. *facepalm*
<thoughtpolice>
But that does seem to be the right track and was my original thought; blackbox it somehow
<ravenexp>
is there any timeline for yosys 0.8 release?
<daveshah>
ravenexp: I think I heard some time over the summer.
<ravenexp>
it seems like it went from 1/2 years between releases to 1 1/2 years
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<dmin7>
hmm, so i did some SPI debugging. seems picosoc starts to read the flash from offset 0 and then stops after about 130kB and then nothing happens ever thereafter ..
<tpb>
Title: [VeriLog] /* * PicoSoC - A simple example SoC using PicoRV32 * * Copyright (C) 201 - Pastebin.com (at pastebin.com)
<dmin7>
went down to 2mhz for testing
<daveshah>
dmin7: looks fine to me
<dmin7>
i do get a 2mhz clock and it looks quite stable on my DSO Quad mini x)
<daveshah>
Can you post a LA trace including CS please?
<dmin7>
LA trace?
* dmin7
rather new to the whole of this :)
<daveshah>
Logic analyser trace - like before, but also with chip select
<dmin7>
oh, good question .. i don't have it in there because last time it wouldn't let me flash anymore when i connected the CS to the logic analyzer too
<dmin7>
which might be a hint that there is sth wrong with CS? x)
* dmin7
go try again
<dmin7>
yip, does not like to be connected to the LA
<dmin7>
(the whole test setup is a bit of a mess atm because i had to connect everything with cables, but i guess if it works for the CLK etc it shouldn't be problem for CS either, already tried switching the gpio pin on the pi and using a different cable for CS)
<daveshah>
That seems a bit weid
<daveshah>
Is this an icoboard or an icezero again?
<dmin7>
icezero
<daveshah>
So no MachXO involved then
<dmin7>
yes
<dmin7>
it works when i put 460ohm resistor before the LA :o
<daveshah>
Just thinking, reading 130kB from flash 0x0 sounds suspiciously like the fpga loading its bitstream
<daveshah>
Oh interesting
<dmin7>
shouldn't those inputs be high impedance?
<dmin7>
with working i mean i can make a trace, not that it runs (:
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<daveshah>
Yes, they should be
<daveshah>
It might be the LA's capacitance causing issues
<daveshah>
Or possibly even a bad pin assignment on CS, so it's floating?