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cr1901_modern >
(Rhetorical) Is it normal for "icebox_vlog -l" to get the pin numbers completely wrong?
13:09
<
cr1901_modern >
_none_ of them match the pcf
13:13
<
cr1901_modern >
Oh I see, my icebox_vlog is too old
13:16
<
daveshah >
yes, just fixed that a few days agp
13:16
<
daveshah >
you can now tell it the package
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<
cr1901_modern >
And post-PAR synth
_also_ suggests my design should work
13:26
<
cr1901_modern >
fabulous. I have no way to debug this
13:27
<
cr1901_modern >
I'm really sick of getting in over my head. What am I supposed to do, decap and read the voltages w/ a FIB?
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tinyfpga_ >
cr1901_modern: do you have your project online anywhere?
15:38
<
cr1901_modern >
tinyfpga_: Yes, I do. Lemme push changes
15:38
<
cr1901_modern >
I have one last thing I can try before I'm truly stumped. But of course it's the most effort
15:39
<
cr1901_modern >
I'll do what ZipCPU does and put a logic analyzer inside (or something that can control the clock one cycle at a time)
15:41
<
tpb >
Title: GitHub - cr1901/misoc-lm32-sim: Testing LiteX LM32 SoCs for bugs using Verilog simulation. (at github.com)
15:41
<
cr1901_modern >
git submodule update and then "make TARGET=tinyfpga-soc-no-trigger"
15:42
<
cr1901_modern >
You will get 3 .vcd files as output- one pre-synthesis, one post-synthesis, and one post-PAR
15:42
<
cr1901_modern >
I never get uart output when I load this bitstream to FPGA
15:42
<
cr1901_modern >
but it works in all simulations
15:44
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tinyfpga_ >
cr1901_modern: ok, I’ll try and take a look at it today
15:49
<
tinyfpga_ >
cr1901_modern: which board are you using? A B2 or BX prototype? I can remember what I sent your way.
15:50
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tinyfpga_ >
cr1901_modern: what were you using for UART to USB?
15:50
<
cr1901_modern >
I broke out pins 5 and 6 for another UART
15:50
<
cr1901_modern >
(for now anyway)
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tinyfpga_ >
cr1901_modern: what device where you connecting to the B2 to perform UART to USB conversion?
15:54
<
cr1901_modern >
prolific FTDI cable
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tinyfpga_ >
cr1901_modern: can you send a link to the product page?
16:03
<
tpb >
Title: USB to TTL Serial Cable - Debug / Console Cable for Raspberry Pi ID: 954 - $9.95 : Adafruit Industries, Unique & fun DIY electronics and kits (at
www.adafruit.com )
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mithro >
Does anyone know if the models output by icetime have implementations anywhere?
23:33
<
mithro >
anyone know if there is a way to stop yosys rotating the inputs on of a lut when outputting to a blif?
23:35
<
mithro >
I'm assuming it is happening because of "synth_ice40 -nocarry; ice40_opt -unlut; abc -lut 4"
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