clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
philtor has joined #yosys
philtor has quit [Ping timeout: 260 seconds]
dxld has quit [Quit: Bye]
dxld has joined #yosys
ravenexp has quit [Ping timeout: 256 seconds]
ravenexp has joined #yosys
sklv has quit [Remote host closed the connection]
sklv has joined #yosys
subuk has joined #yosys
promach_ has joined #yosys
maartenBE has quit [Ping timeout: 256 seconds]
subuk has quit [Ping timeout: 260 seconds]
maartenBE has joined #yosys
pie_ has quit [Ping timeout: 268 seconds]
philtor has joined #yosys
philtor has quit [Ping timeout: 240 seconds]
pie_ has joined #yosys
pie_ has quit [Remote host closed the connection]
roh has joined #yosys
philtor has joined #yosys
promach_ has quit [Quit: WeeChat 2.1]
leviathan has joined #yosys
xerpi has joined #yosys
leviathan has quit [Ping timeout: 240 seconds]
leviathan has joined #yosys
dys has joined #yosys
xerpi has quit [Quit: Leaving]
sklv1 has joined #yosys
sklv has quit [Ping timeout: 250 seconds]
sklv1 has quit [Ping timeout: 250 seconds]
sklv1 has joined #yosys
m_t has joined #yosys
jwhitmore has joined #yosys
_whitelogger has joined #yosys
promach_ has joined #yosys
ZipCPU|ztop has joined #yosys
<cr1901_modern> (Rhetorical) Is it normal for "icebox_vlog -l" to get the pin numbers completely wrong?
<cr1901_modern> _none_ of them match the pcf
<cr1901_modern> Oh I see, my icebox_vlog is too old
<daveshah> yes, just fixed that a few days agp
<daveshah> *ago
<daveshah> you can now tell it the package
jwhitmore has quit [Ping timeout: 264 seconds]
ZipCPU|ztop has quit [Ping timeout: 256 seconds]
<cr1901_modern> And post-PAR synth _also_ suggests my design should work
<cr1901_modern> fabulous. I have no way to debug this
<cr1901_modern> I'm really sick of getting in over my head. What am I supposed to do, decap and read the voltages w/ a FIB?
xerpi has joined #yosys
m_t has quit [Quit: Leaving]
<tinyfpga_> cr1901_modern: do you have your project online anywhere?
<cr1901_modern> tinyfpga_: Yes, I do. Lemme push changes
<cr1901_modern> I have one last thing I can try before I'm truly stumped. But of course it's the most effort
<cr1901_modern> I'll do what ZipCPU does and put a logic analyzer inside (or something that can control the clock one cycle at a time)
<cr1901_modern> tinyfpga_: https://github.com/cr1901/misoc-lm32-sim
<tpb> Title: GitHub - cr1901/misoc-lm32-sim: Testing LiteX LM32 SoCs for bugs using Verilog simulation. (at github.com)
<cr1901_modern> git submodule update and then "make TARGET=tinyfpga-soc-no-trigger"
<cr1901_modern> You will get 3 .vcd files as output- one pre-synthesis, one post-synthesis, and one post-PAR
<cr1901_modern> I never get uart output when I load this bitstream to FPGA
<cr1901_modern> but it works in all simulations
<tinyfpga_> cr1901_modern: ok, I’ll try and take a look at it today
<tinyfpga_> cr1901_modern: which board are you using? A B2 or BX prototype? I can remember what I sent your way.
<cr1901_modern> B2
<tinyfpga_> cr1901_modern: what were you using for UART to USB?
<cr1901_modern> I broke out pins 5 and 6 for another UART
<cr1901_modern> (for now anyway)
<tinyfpga_> cr1901_modern: what device where you connecting to the B2 to perform UART to USB conversion?
<cr1901_modern> prolific FTDI cable
<tinyfpga_> cr1901_modern: can you send a link to the product page?
<cr1901_modern> tinyfpga_: https://www.adafruit.com/product/954
<tpb> Title: USB to TTL Serial Cable - Debug / Console Cable for Raspberry Pi ID: 954 - $9.95 : Adafruit Industries, Unique & fun DIY electronics and kits (at www.adafruit.com)
roh has quit [Ping timeout: 265 seconds]
develonepi3 has joined #yosys
promach_ has quit [Quit: WeeChat 2.1]
dys has quit [Ping timeout: 256 seconds]
roh has joined #yosys
tinyfpga_ is now known as tinyfpga
dys has joined #yosys
leviathan has quit [Ping timeout: 268 seconds]
roh has quit [Ping timeout: 240 seconds]
roh has joined #yosys
dys has quit [Ping timeout: 260 seconds]
jwhitmore has joined #yosys
jwhitmore has quit [Remote host closed the connection]
xerpi has quit [Quit: Leaving]
gnufan1 has quit [Ping timeout: 256 seconds]
gnufan has joined #yosys
emeb has joined #yosys
danieljabailey has quit [Quit: ZNC 1.6.5+deb2build2 - http://znc.in]
danieljabailey has joined #yosys
<mithro> Does anyone know if the models output by icetime have implementations anywhere?
<mithro> anyone know if there is a way to stop yosys rotating the inputs on of a lut when outputting to a blif?
<mithro> I'm assuming it is happening because of "synth_ice40 -nocarry; ice40_opt -unlut; abc -lut 4"
tpb has quit [Remote host closed the connection]
tpb has joined #yosys