<tpb>
Title: UART/test_UART.v at development · promach/UART · GitHub (at github.com)
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<ZipCPU>
No, promach_: it should be just find for induction.
<promach_>
ZipCPU: but I really doubt, because $past(variable) could be of anything in induction, right ?
<ZipCPU>
The only issues are that it will only work in a clocked always block, the "erroneous" trace will appear on the second to the last clock, and who knows what past references on the very first time step during induction.
<ZipCPU>
(You'll have to recover from that first timestep in the following time steps)
<promach_>
ZipCPU: but I am using $past(variable) on the condition for assert(variable) in induction
<ZipCPU>
Yes, that was what I thought I was talking about.
<ZipCPU>
I do it all the time.
<promach_>
hmm... probably I should look for the induction bug at some other place in my code then
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<azzizi>
Hi can anyone please tell me if the 'passes' can be written in python ? or using c++ is a must?
<azzizi>
To clarify passes on the RTLIL
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<ZipCPU>
azzizi: I would imagine they could be written in Python, don't see why not, however you might need to build your own patched infrastructure to make that happen.
<azzizi>
could you please elaborate on 'patched infrastructure' a bit more ? Not getting that
<azzizi>
e.g. i would like to add some things on the RTLIL suppose say with python ...what are the things to keep in mind
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<ZipCPU>
My point is specifically that the current infrastructure doesn't include python. You would need to connect your pythong code to yosys yourself.
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