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<promach_>
Can SymbiYosys support wildcard files selection yet ?
<promach_>
and does Yosys support any automated bug insertion (mutation) methodology ?
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<gyroninja>
Hi, I'm having trouble synthesizing a design I've made. It removes all the cells during optimization leaving me with 0 cells total in the end. This is likely me to either using yosys wrong or verilog wrong as I'm a newbie at both. I've created a small test program which exhibits the behaviour I'm talking about: https://hastebin.com/tiwiwiqagi.v If I use use verilator to simulate the design, it seems to work
<gyroninja>
fine (the data output is toggled).
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<gyroninja>
I've also tried on both version 0.7 and the latest from git
<ravenexp>
data is not a reg
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<ravenexp>
you can't parallel assign a value to a wire
<gyroninja>
thanks
<ZipCPU>
You might also wish to look into the "show" command. It works great on small designs to illustrate a logic flaw, but ... can be difficult to use with really large designs.
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<gyroninja>
After messing around with it for a while, I still haven't been able to figure out what I did wrong. I tried declaring my output as reg and switching = and <= around, but it didn't help. I did notice that if it seems to work fine if I use an if statement / conditional operator to set my output instead of from an array. https://hastebin.com/erohufariv.v <- Is my broken code that doesn't generate any cells. If
<gyroninja>
you uncomment the commented line and comment the one below it, it seems to work.
<ZipCPU>
gyroninja: Start at the top again ... what are you tring to do?
<ZipCPU>
*trying
<ZipCPU>
Looking over your code, I noticed you declared an array of one element: reg [0:0] array[2];
<ZipCPU>
Did you mean to do that, or were you trying to do: reg [0:0] array [0:1]; ... an array of two elements?
<ZipCPU>
Also, as a matter of general practice, most synthesizers don't recognize arrays from block RAM elements if anything else is with them within their always statements.
<ZipCPU>
Hence, I think you wanted: always @(posedge clock) data <= array[index]; always @(posedge clock) index <= !index;
<tpb>
Title: Binary multiplier - Wikipedia (at en.wikipedia.org)
<ZipCPU>
A very strange algorithm to debug. I think I misread the description incorrectly several times over.
* ZipCPU
now has it working through an exhaustive simulation via verilator.
<gyroninja>
ZipCPU: I want to essentially look up a value from the array
<gyroninja>
and assign it to the output
<ZipCPU>
Yeah, you have your array declared incorrectly.
<gyroninja>
Isn't it an array of 2 elements though?
<gyroninja>
of 1 bit each
<ZipCPU>
Not if you declare it as: reg [0:0] array [2];
<ZipCPU>
You need to declare an array of two one-bit elements as: reg [0:0] array [0:1];
<gyroninja>
Doing it the way I've been doing it works fine with Verilator
<gyroninja>
but yet doing it your way makes it generate cells
<gyroninja>
and fixes the problem
<ZipCPU>
Ahm ... I doubt it was really working with Verilator.
<gyroninja>
It was though
<ZipCPU>
If you dig into code like that, you'll often find Verilator reading from unallocated memory
<ZipCPU>
Where it gets really bad is when you try to write to that memory, and then overwrite something on your stack or something
<gyroninja>
Well something to point out is that it at least recognized it as an array
<ZipCPU>
Absolutely! You told it that it was an array of one element.
<gyroninja>
If I tried to assign into an element beyond the second element it would warn me and not compile
<ZipCPU>
Then, you initialized two elements that weren't in the array.
<gyroninja>
If I declare it with [2] and try to assign to array[2] the warning I get from verilator is: "%Warning-SELRANGE: test.v:13: Selection index out of range: 2 outside 1:0"
<gyroninja>
Notice how it seems to be interpreting the 2 as 1:0 for me
<ZipCPU>
Fascinating.
<ZipCPU>
Not quite what I was expecting--what does the C++ generated code look like? Should be easy enough to interpret.