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<Ank>
Hi all, one questions regarding synthesis with Yosys. Does yosys windows version follow all the synthesis command based constraints? like clock, pin out loading, etc?
<Ank>
It seems to ignore them.. may be this is with windows version? should we switch to linux ?
<ZipCPU>
Ank: Is there a yosys windows version?
<ZipCPU>
If so .... I can't imagine why it would be any different
<ZipCPU>
Do you have all the dependencies set up properly?
<tpb>
Title: Yosys Open SYnthesis Suite :: Download (at www.clifford.at)
<Ank>
The webpage also says - At the moment Yosys is mostly tested on Linux.
<ZipCPU>
This is most certainly true.
<ZipCPU>
I know most of the developers spend all their time on Linux.
<Ank>
It is working fine.. it gives out synthesized netlist.. but somehow it is not following the constraints
<ZipCPU>
Which constraints is yosys not following?
<Ank>
Like a higher clock rate synthesis..
<ZipCPU>
Such as ... ?
<Ank>
or output pin loading
<ZipCPU>
yosys doesn't handle output pins ... that's handled by the placement tool. Yosys itself only does synthesis
<Ank>
Yeah, correct. But, will it set sufficient buffering for the pin loads or not?
<Ank>
there are commands where you can set the output pin loads...
<Ank>
during synthesis
<ZipCPU>
Yes/no. It may or may not connect the pins to IO cells. If you connect the pins to an SB_IO block (iCE40), that usually handles any needs you might have.
<ZipCPU>
What yosys doesn't handle (well) are inout ports.
<ZipCPU>
I've got to imagine that such ports are on the "to-do" list, although they've been on the same to-do list for quite some time by now.
<Ank>
Now, I think that my concerns are more related to ABC
<ZipCPU>
If you instantiate an SB_IO primitive you get access to that capability without much hassle.
<tpb>
Title: Yosys Open SYnthesis Suite :: Command Reference :: abc (at www.clifford.at)
<Ank>
there is -constr file.. in which one can set driving cell and load
<ZipCPU>
Most people have no need to work with abc apart from the default yosys settings. What is it you are trying to do?
<Ank>
then, there is -D flag with which one can set delay target.. which is linked to clock rate
<ZipCPU>
What hardware are you working with?
<Ank>
it is for ASIC
<Ank>
no fpga hardware
<ZipCPU>
Ahh ... okay. And what functionality are you hoping to get from the synthesis tool that it isn't providing?
<Ank>
The delault synthesized output is good for lets say 40Mhz clock.. but it is slow for 125MHz.
<Ank>
I want to speed up the delays in the synthesized netlist so it can clock it at higher frequencies.
<ZipCPU>
Are you sure that's the synthesizer's fault and not the fault of your layout?
<ZipCPU>
If you are sure, then ... yeah, abc might be the place to look.
<Ank>
Yes, not reached the layout phase yet.. just doing simulations at gate level netlist
<ZipCPU>
I didn't think the gate level netlist had any timing properties associated with it ... ??
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<Ank>
The timing comes from the gates inserted in the paths right? Instead of using inv1x strength, if it would use inv4x strengths, the delays will be less. Just saying..
<daveshah>
Ank: are you sure your design is able to reach 125MHz?
<Ank>
These are real fooundry provided gates,, so one can so spice simulations of the synthesized netlist
<Ank>
one can *do
<daveshah>
Yeah, but your logic could still be too slow for abc to find any way to synthesise it above 40MHz. Is it proven with anything else?
<Ank>
No, it is a very small core of may be 1000 gates
<daveshah>
If it is, this could be an issue passing stuff to abc as you initially thought. I would definitely try and test on Linux which is what most people test on.
<Ank>
it can definitely do above 200MHz that I know
<Ank>
I must check it then on a linux platform
<daveshah>
So I'd say either Yosys is calling abc incorrectly for some reason, or it is a bug in abc
<Ank>
If anyone has faced similar problems on windows platform, then please let me know
<noname_Matt>
is there anywhere that goes into detail about how a pnr like arachne works? (other than reading the code itself, of course)
<noname_Matt>
I'm interested to know
<ZipCPU>
noname_Matt: You might have better luck asking the question. I might be able to help with the placer portion of that. daveshah would also know.
<noname_Matt>
I don't have a specific question, I just want to know more about how place and route is done.
<noname_Matt>
Since I know basically zilch.
<ZipCPU>
Let me try to describe the placer for you ... it'd be good a good exercise for me
<noname_Matt>
ok
<ZipCPU>
The placer works by picking FPGA array elements, and assigning them to logic elements within your design. It does this in multiple passes. The first pass tends to be just a random mapping.
<ZipCPU>
Then, the placer examines the mapping, and randomly changes some of the assignments--using over all wire length as a metric it tries to minimize.
<ZipCPU>
By using a form of simulated annealing, it can juggle fewer and fewer changes until (hopefully) everything ends up better than it was before with a "decent" design.
<tpb>
Title: Simulated annealing - Wikipedia (at en.wikipedia.org)
<noname_Matt>
ah. this might require more sleep
<ZipCPU>
It's an old AI trick for trying to find a result in a space of possibilities that are much to big to properly search. Annealing works by modifying an existing placement to see if you can't make a better one.
<ZipCPU>
The size of the modifications are adjusted over time, starting with big adjustments, working towards little ones.
<noname_Matt>
I have probably goeen really good at doing the exact same thing in minecraft in 3D :)
<ZipCPU>
Imagine the logic elements to be places where a kernel of popcorn might end up in a pan after popping. Initially, everything is moving. Slowly, as the kernels pop, things slow down.
<noname_Matt>
I sometimes play a modded version with nuclear reactors and such, and it's always a struggle to fit all my pipes and wires and such into the rooms I build, which are never big enough
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<ZipCPU>
I'm trying to avoid playing with nuclear reactors myself ... I just wouldn't trust my lack of experience to be able to keep the thing from having some sort of exothermic event
<noname_Matt>
I would have thought you could work out the best placement purely from the logical net itself
<ZipCPU>
How so? Please go on.
<noname_Matt>
something like get it to lay flat and pull the pieces together
<ZipCPU>
If you have a good idea, ... I might even try it! ;)
<noname_Matt>
from the logic, net you might be able to figure out what stuff has to be closer to other stuff, since the components of a single multiplexer should be close together, with short wires inbetween
<ZipCPU>
True, but what if multiple things want the result of that multiplexer?
<ZipCPU>
Then you have one output that needs to feed many inputs.
<noname_Matt>
there might be some long wires in the design, like clocks, which touch stuff in distant places, but those are single connections outweighed by lots of ones that want to be small local ones
<noname_Matt>
the main issue I see with this is this sort of information might be obscured by logic sysnthesis
<ZipCPU>
Clocks tend to have their own networks, so ... not usually a big deal yet.
<ZipCPU>
As for obscured, yeah ... it is somewhat, but it shouldn't be too hard to unobscure and recapture.
<noname_Matt>
well, the clock is a general example, any signal that crosses from one end to the other would be like that
<ZipCPU>
How about a data bus? That's a good example IMHO.
<noname_Matt>
yeah
<noname_Matt>
those would be a pain
<ZipCPU>
Every slave connected to the bus will need a connection.
<noname_Matt>
that's something *you* would know has to be long and connect to lots of far away stuff, but it has a lot of wires
<noname_Matt>
so it would tend to pull stuff together that might not be optimal
<noname_Matt>
I suppose in a way I might be walking in a circle towards annealing
<ZipCPU>
Try this ... you can work from a FF with a clock edge to another FF with the next clock edge
<noname_Matt>
FF?
<ZipCPU>
(Flip-flop) You can measure the logic between FF's, and so measure how "long" something will take to process.
<ZipCPU>
Your goal would be to make sure that the longest FF chain is kept to a minimum (one-clock period) distance.
<ZipCPU>
Along the way, you can move FF's on this chain.
<noname_Matt>
when you transition from "large" to "small" changes, how do you define large and small?
<ZipCPU>
Logic elements that are drawn together should make it easier for other logic elements in the chain to be farther apart.
<ZipCPU>
Yes.
<noname_Matt>
is it something like moving fewer wire paths less distance, or moving larger blocks of congealed circuitry less?
<ZipCPU>
noname_Matt: It's based upon a score that you are trying to minimize. There's a "diameter" parameter which is used to pick an alternate configuration to a particular placement. As the "temperature" lowers, the diameter gets smaller.
<ZipCPU>
Hence, you look for better LUT placements closer and closer to the last one as time goes on.
<noname_Matt>
but you're always moving LUTs one at a time?
<ZipCPU>
In arachnepnr, yes.
<ZipCPU>
It seems there would be a time and place for tearing up sections larger than a single LUT to replace, but ... that would need to be a future upgrade.
<noname_Matt>
hrm. What I was imaging above was a system where you gradually congeal LUTs into larger and larger groups, and move them as a whole. You basically work up from the bottom saying "It is optimal that these two LUTs be close together, for reason X" then work towards "It is optimal that these two groups of LUTs be close together, for reason X" (which in the design might be two multiplexers with a lot of common connections)
<noname_Matt>
you might still allow breaking up groups, but it would be less and less attractive to split it in half and move the two halfs apart
<noname_Matt>
your reasoning might be based on wire length, for example
<ZipCPU>
That sounds like a possible approach, but how do you know you have the groupings right?
<noname_Matt>
I'm not too sure. You could argue that LUTs that have a lot of connections that are common should be close, since they're probably related. I wonder if starting the annealing by laying things out based on their connections might lead to an "optimal" solution faster
<ZipCPU>
That is a fascinating thought. I might need to try it. :D
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<noname_Matt>
It might be good low hanging fruit for testing this group and logical connection based approach
<noname_Matt>
seeing if it has any merit
<noname_Matt>
All I can say is it works pretty good in minecraft (I've gotten out of some pretty tight scrapes) but in that case I have knowledge of the overarching design
<ZipCPU>
Yes it might. I'm definitely going to think about it.
<ZipCPU>
What happens if the design elements don't really lay out in a even grid fashion?
<noname_Matt>
I can even "resynthsize" things a little ,(to something "logically equivalent") if I find some connections to be very inconvenient
<noname_Matt>
well, you will probably always have connections that will span the design
<noname_Matt>
crossing over stuff
<noname_Matt>
so it won't lay flat
<noname_Matt>
you probably want to just get as flat as possible, and you might not have to do it in a super smart way, since you're optimising afterwards
<noname_Matt>
you probably want to just get as flat as possible, and you might not have to do it in a super smart way, since you're optimizing afterwards
<noname_Matt>
oops
<noname_Matt>
My instincts, having never done anything like this, would be to actually place and rout and synthesize at the same time, laying out large logical blocks (and trusting the human to have them separated by function in an intelligent manor) and then trying to pencil in their contents as I move towards something that could actually be put on the FPGS
<noname_Matt>
this is probably stupid though
<noname_Matt>
the reason I think it's dumb is that it's entirely possible that what makes conceptual sense makes no sense at all from a layout perspective. in a schematic, you can have busses and wires as long as you want
<noname_Matt>
and can group functinoality however you want
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<ZipCPU>
"My instincts, having never done anything like this" before ... neither have I. I might want to try it anyway though.
<noname_Matt>
darn. I need to break the habit discord has taught me of uparrow-ing to fix errors after the fact
<ZipCPU>
No, but I like your thought of grouping small things into larger things.
<ZipCPU>
Then moving larger things around.
<noname_Matt>
don't forget rotating
<ZipCPU>
And squishing
<noname_Matt>
you may need to deform a group to make it fit nicer, or rotate it, or reflect it
<ZipCPU>
There are a lot of things that might end up happening to that larger piece of design along the way as attempts are made to place it.
<noname_Matt>
I would take a dumb approach to that
<ZipCPU>
What would that approach be?
<noname_Matt>
if a bunch of signals are on the wrong side, flip it and remeasure the score. take the one that's lower. that sort of thing
<ZipCPU>
What happens if you have two puzzle pieced elements, but with the wrong connection shape?
<noname_Matt>
supporting deformation would be a nice goal, but for that you probably need to think about the groups inside the groups
<noname_Matt>
to take one example I might be able to suggest a solution for, suppose you have two groups, with an interface inbetween
* ZipCPU
listens
<noname_Matt>
and theres something inconvenient, like two buses that cross over each other
<noname_Matt>
the "smart" way I would do it, being human, would be to look at each group and look a the sub groups that generate the busses
<daveshah>
noname_Matt: in an FPGA architecure, I don't believe the penalty for crossing over is too great. It is total wirelength that is most important
<noname_Matt>
can I move one up and the other down? does this affect anything else in the toplevel group
<ZipCPU>
The big problem you will have is when you hit the borders of the array--in addition to the deformation problems we just discussed.
<noname_Matt>
this becomes a recursive thing, where every time you bump into something "inconvenient" (some contribution to a rise in unpleasantness, however you measure it), you check the next level down to see if adjust ments can be made
* ZipCPU
notes that daveshah has been maintaining arachnepnr, and might know more about its functionality than ZipCPU does
<noname_Matt>
this could quickly husr preformance though
<noname_Matt>
hurt*
<noname_Matt>
I suppose you'd need some sort of "to heck with it, I don't want to go any deeper" kind of thing
<noname_Matt>
and that limit would get stricter as the blocks get bigger
<daveshah>
So, is quite an interesting idea for bigger fpgas where the simple simulated annealing approach that looks at each cell is too slow
<ZipCPU>
I'm going to have to think on this possibility. I mean, there are many ideas here. I'm not sure if they work, but I'm really tempted to think about and perhaps even try some of them.
<noname_Matt>
*I* certainly wouldn't want to spend time unraveling my own work
<ZipCPU>
But you'll have to.
<daveshah>
You would probably only want to do the block based stuff early on, then do fine grained placement at individual cell level later in the placement
<ZipCPU>
I've got designs that are close to 95-98% full. You have to get every last LUT to fill, and you have to deform molecules if you have them.
<noname_Matt>
well, I wouldn't want to spend too much, unless there was some indication I could massively reduce unpleasantness
<ZipCPU>
Still, this might be used to guide some initial placement decisions.
<noname_Matt>
I don't have a heuristic for whether something *might* reduce unpleasantness, since IRL I usually just try it and see hot it goes
<noname_Matt>
how*
<ZipCPU>
So .... you weren't trying to make a simulated annealing pun?
<daveshah>
noname_Matt: the heuristic arachne-pnr uses is simply total wirelength
<ZipCPU>
;)
<daveshah>
Basically, for each wire it looks at the locations it connects to and calculates distance between them
<noname_Matt>
pun unintended
<daveshah>
But a more serious tool would configure timing information in that metric too
<noname_Matt>
makes sense
<daveshah>
Wires that are part of a long timing path (many cells between DFF output and input) must be considered more important than those in a short timing path
<daveshah>
The lack of this in arachne-pnr means its timing values are quire unpredictable and maybe 30% worse than a timing driven tool
<noname_Matt>
sadly, I think a lot of useful information is lost in synthesis regarding what paths are and are not timing-critical
<daveshah>
No, definitely not
<noname_Matt>
you may have long paths (ie debugging) for which it's not super important
<daveshah>
These will still ruin your day if they don't meet timing though
<daveshah>
Unless they're just straight to IO without going through registers
<daveshah>
In either case, a proper tool would let you add constraints to ignore these paths if you really want
<daveshah>
And manually constraint other things that are needed
<noname_Matt>
perhaps I have an overly simplistic understanding of synthesis
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<noname_Matt>
still, as I noted above, you might be able to get hints from the human regarding the initial block divisions, if you knew things about how the levels of the design are structured
<noname_Matt>
ideally, receiving a tree where each level is logically equivalent
<noname_Matt>
but the top is the design as the human sees it, and at the bottom are just LUTs
<awygle>
also, arachne doesn't just use total wire length. it uses an approximation, because you can't get a real number without routing the design. it uses half perimeter wire length as that approximation.
<daveshah>
noname_Matt: that is what you get if you would synthesise a design without flattening
<daveshah>
But then that precludes a number of synthesis optimisations
<noname_Matt>
you might be able to work with some intermediate: apply the operations and don't care that it might mess up your tagging
<daveshah>
Yes, that's how you'd have to do it
<daveshah>
awygle: one possibility with that is to determine a function based on a large number of designs between distance and delay
<daveshah>
This would probably give a better heuristic to determine delay than just distance based measures as are used at the moment, without excessive performance cost
<awygle>
yes, a straightforward "Manhattan distance to delay" approach is common
<awygle>
it's fast as it's just a table lookup
<awygle>
at least one of the papers I have on the openfpga wiki does that, and there's a discussion of how to add the time parameter and keep the cost function stable and whatnot
<daveshah>
Interesting
<daveshah>
I would also like to look at going back to placement if routing finds areas that are congested, have excessive fanout, etc, and can't route them within the timing budget
<noname_Matt>
That's the kind of scenario I imagine shifting whole blocks of LUTs over might be helpful
<awygle>
That's tricky as routing is potentially expensive. I believe I read a paper where the full route was run every N iterations of the placer, and then that value was added to the wire cost with some kind of decay
<awygle>
But I'd have to dig it up
<awygle>
But yes in general by breaking the problem into phases we get worse results (but more tractable problems of course)
<awygle>
Ideally synthesis, packing, placement, and routing would all be the same process (or continually feed back into each other which is the same thing)
<daveshah>
Yes, that would also be needed for doing stuff like cell duplication for high fan out but simple logic
<awygle>
Yup. It's an interesting set of problems even before you bring in parallelism. Anyway :-P it's after midnight here. Goodnight!
<noname_Matt>
Is that where you duplicate the logic generating a signal, if it's cheaper than routing a long wire to where the signals is needed?
* noname_Matt
checks clock: 3:42AM Hrm.
<daveshah>
Yeah, that's the idea
<daveshah>
The most basic example would be a source of constant '1' (single logic cell) on an architecure without constant generators
<noname_Matt>
seems there's a long list of features an arch may or may not have
<noname_Matt>
and then there's the arch of the actual cells and connections
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<noname_Matt>
I can see why trying to build a generalized *anything* is hard
<daveshah>
So the idea would be to have generic place and route functions call into architecure specific functions
<daveshah>
Some stuff, like design legalisation, validity checking and most of packing, is architecure specific
<noname_Matt>
are there any multiarch PnRs?
<daveshah>
Packing actually tends to be vendor rather than architecure specific because most vendors have similar or identical logic cells used in many architectures
<daveshah>
There is VPR, but it is primarily intended for virtual architectures and getting it to work on real FPGAs is quite hard
<noname_Matt>
I think I head about that :)
<daveshah>
NeoCAD is a commercial PnR that underpins Lattice Diamond and Xilinx ISE
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<daveshah>
But no idea how similar the code base is between the two now, they diverged in the late 90s
<noname_Matt>
That's a long time ago
* noname_Matt
was born around then
<daveshah>
Same...
<daveshah>
Would love to mention a few more things now, unfortunately I can't.
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<mjoldfield>
Having flattened the design, can you recover/infer good blocks by doing a minimum k-cut on the connectivity graph ?
<ZipCPU>
What do you mean by "good blocks"? (I feel like I'm coming into the middle of a conversation here ... is this in reference to placing algorithms?)
<mjoldfield>
Yes.
<ZipCPU>
Ok, and what do you mean by "good blocks"? A placer places logic "blocks" into the design. Blocks at that point are neither good nor bad, they are design blocks that need to be placed, right? Or am I missing something?
<mjoldfield>
In the discussion above people were talking about routing small stuff then gluing those together. Then someone pointed out that if you flatten the design you lose the notion of the small blocks, so I wonder if minimum k-cut would recover components which are weakly connected to other blocks.
<tpb>
Title: Minimum cut - Wikipedia (at en.wikipedia.org)
<mjoldfield>
I think there are a bunch of algorithms on graphs which do things more efficiently than you might guess, and they seem relevant for routing problems. However, I don't know much more about graph theory than 'there be interesting results here'.
<ZipCPU>
I suppose that's about as much as I know as well, but I like your link, and I'll do some reading on it.
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<mjoldfield>
I hope it's helpful. Let me know if you get anywhere.
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<noname_Matt>
What's the largest contiguous ram you could specify in something like an ICE40HX8K? Or is it impractical for a large block of ram to coexist with other logic?
<noname_Matt>
(from a pnr standpoint)
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