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<roamingryan>
Are single line `assign` statements the only way to avoid the "assigned in a block at..." warning with Yosys?
<mwk>
if you assign something in a block, the proper thing to do in verilog is to declare it as "reg", not "wire"
<mwk>
yosys grudgingly accepts misuse of that, but other tools will flat-out refuse to work
<roamingryan>
I see... even though I want it synthesized as combinatorial logic?
<mwk>
yes
<mwk>
reg/wire distinction is not about combinatorial or synchronous logic, it's about whether it's assigned from a process or not
<mwk>
(verilog is not a particularly well-designed language)
<roamingryan>
Interesting, this is a great to know.
<roamingryan>
So, put differently, one shouldn't scan the input/output ports of a given module and assume that `reg` output pins are registered?
<mwk>
correct
<roamingryan>
That's fun. Thank you for sharing some wisdom. :)
<mwk>
reg output pins can be combinatorial, assigned in a combinatorial process; non-reg output pins can be synchronous if they happen to use assign statements (or submodule instantiations) to bring out the result of a synchronous process defined somewhere deeper
<roamingryan>
Great to know. The module I am implementing requires slightly more logic at an output pin than can be accomodated with a simple ternary assignment operator. I also don't want some sort of nasty nested ternary operator. Hence my question above. Sounds like switching the pin to `reg` and using an `always (*)` block with blocking assignments (`=`) is the way to go.
<mwk>
correct
<mwk>
also please consider using other tools than yosys to check your code, yosys is, uh, good at processing correct code, not so good at diagnosing incorrect code
<roamingryan>
verilator?
<mwk>
yeah, it'd be good to run it through some simulation
<mwk>
verilator or iverilog
<mwk>
whichever you prefer
<roamingryan>
Ok, so far I've been developing purely with yosys and symbiyosys using a "formal first" methodology. I'll get some verilator sims set up in parallel.
<mwk>
that's not a bad plan
<mwk>
but it'd be good to at least run it through a linter
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<mwk>
verilator --lint-only
<roamingryan>
Cool, I'll give that try and see what sort of horrors it reveals. No doubt there will be some!