clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
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<nick_> Would anyone be able to point me towards documentation about the timing specs of ICE40HX parts?
<daveshah> With the Makefile in that folder you can also create a HTML version of that file that's a bit more readable
<nick_> Thanks
<nick_> Do you know where the data comes from?
<nick_> Was it from testing devices, or some other docs?
<daveshah> It comes from parsing sdf files generated by icecube
<daveshah> In practice, those numbers are very conservative and actual performance at room temp will be quite a bit faster
<nick_> OK
<nick_> I'm not too worried about absolute values, but in comparing some timings.
<nick_> Like how much faster the carry chain is than going through LUTs
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<corecode> daveshah: you think it is possible that the ice5lp1k don't have the additional (to 4k) bram accessible?
<daveshah> It's theoretically possible, but also unlikely, imo
<corecode> daveshah: or is it possible that i made a mistake in the port, and even the 4k chip wouldn't work
<daveshah> Thats also possible
<corecode> my mistakes are likely
<corecode> i wonder how to test this without a 4k chip
<daveshah> Create a design with all the ram in icecube and see if icebox_vlog reports anything suspicious?
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