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<bjorkintosh>
tnt> Basically you use the vendor tools, generate a very simple design, look at the output, tweak a small thing, compare the new output to the previous one, repeat.
<bjorkintosh>
how do you know when you've completed such a task?
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<roamingryan>
I think the goal is to understand the function of every single bit in the bitstream.
<mwk>
the goal is to get reasonably full coverage
<bjorkintosh>
sounds like a machine learning(TM) AI (LOL_Buzzword) task!
<mwk>
"every single bit" is unrealistic, mostly due to craploads of test-only bits that are basically useless unless you're factory-testing a bare die
<bjorkintosh>
of course, that's just hand waving.
<bjorkintosh>
mwk, ah. is there a guide line? I have an old xilinx I'd like to make some use of.
<mwk>
no
<mwk>
reversing FPGAs is not a common task
<mwk>
there are no guidelines
<bjorkintosh>
hmm.
<mwk>
and this kind of project takes months or years
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<bjorkintosh>
of course.
<bjorkintosh>
yosys only does verilog now, right?
<bjorkintosh>
no vhdl?
<mwk>
there's a ghdl plugin
<mwk>
which is apparently workable
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<thoughtpolice>
Is the yosys-bot auto-commit currently offline? It hasn't committed an updated tag since Feb 17th. (Just curious and not like, a rush or anything.)
<mwk>
... I'll ask the responsible people
<mwk>
but yes, it should be commiting
<mwk>
so it presumably broke
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<thoughtpolice>
ty! I maintain a package for Yosys and just like using those tags as the version number for the package. Was curious today and saw it hadn't happened.