clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
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<jfierro> Hey all. Does anybody know what modulus semantics verilog is supposed to follow?
<jfierro> Example, should -98 % 8096 = 7998?
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<lambda> aww man, that would've been *the* question for me, but they disconnected
<lambda> (and no, $mod(-98, 8096)==-98, $modfloor(-98, 8096)==7998)
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<jfierro> Hey lamba I  saw your response, thanks.
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