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<cr1901_modern> azonenberg: For KiCAD projects, is there a recommended location to place external schematic parts and footprints, so if a person on another computer opens your project file, they will be able to manipulate/place the new parts without error?
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<azonenberg> Good question
<azonenberg> ask in #kicad
<azonenberg> I use more absolute paths than i should :P
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<cr1901_modern> azonenberg: I'm mildly amused that you don't hang out in #kicad, despite being a kicad dev lol
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<nats`> cr1901_modern the kicad channel is pretty boring
<nats`> I use it since years but the channel is mainly a corner for grumpy people
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<cr1901_modern> azonenberg: Why doesn't kicad keep wires connected when I move components?
* cr1901_modern 's "principle of least surprise" is being heavily violated here...
<nats`> they never implemented the "sticky" wire
<nats`> TBH it's not a bad
<nats`> I see how it's implemented in cadence and mentor and it's really usable
<nats`> not
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<cr1901_modern> I guess it's fine if you only place components once and never move them :)
<cr1901_modern> Well, at least moving wires+component will automatically reconnect to another component as well
<azonenberg> nats`, cr1901_modern: There *is* an option to do that
<azonenberg> i think shift or ctrl while dragging?
<azonenberg> I also *do* hang out in #kicad, but only when doing active dev myself
<cr1901_modern> azonenberg: I see
<cr1901_modern> And yes, ctrl did it
<cr1901_modern> Still getting used to the fact that to select components I have to drag slightly/capture a single part in a square
<cr1901_modern> Oh I see now... you're supposed to use the mouse in tandem w/ keyboard to do tasks
<azonenberg> That's the typical UI model, yes
<azonenberg> mouse to position, keyboard to operate
<azonenberg> To move a single component, mouse over it then hit M
<azonenberg> That's how i normally do it
<azonenberg> Only time i drag is for multi-select
<cr1901_modern> Finally figured that out
<cr1901_modern> In any case, I think I figured out a small minimal-component Lattice board, so trying that
<cr1901_modern> azonenberg: Is it possible to have the same part on two different sheets? So, I can divide sheets by purpose, such as putting all the filter caps on one sheet
<azonenberg> The same physical component
<azonenberg> Or, sub-components of a multi-part
<azonenberg> The latter, yes
<cr1901_modern> the same sub-components of a multi-part
<azonenberg> I typically put power/ground pins on a separate sub-component for that exact reason
<azonenberg> The same sub-component, no
<azonenberg> Different sub-components can be spread out as you see fit
<azonenberg> Typically for small-mid sized stuff i have one sub-component with power/ground
<cr1901_modern> okay then... I just lost an entire side of the FPGA to the FT245 interface lol
<azonenberg> for larger i do one power and one ground
<azonenberg> Typically what I do is have one sub-component per IO bank
<azonenberg> and try to keep the banks be one or two functional subsystems
<azonenberg> then put all of that on one sheet
<azonenberg> or have the FPGA+one subsystem on one sheet, and a few pins going to another sheet for the other subsystem
<cr1901_modern> Fair enough. That's what I'll do then.
<cr1901_modern> Idk if Xilinx has this, but Lattice has the ability to load a bitstream as slave SPI from a computer. My idea was to put FT245 into bit-bang mode, feed an FPGA my bitstream, and then swap to queue mode
<cr1901_modern> the SPI pins can be repurposed as IO, so I wanted all this functionality on the same side (the bottom of the LQFP chip).
* cr1901_modern has a feeling a number of pin assignments are going to change when layout actually starts
<azonenberg> Xilinx can load in slave SPI but why would you do that when you could do JTAG which has more advanced features (like readback and stuff)?
<azonenberg> FT232H can do JTAG easily
<azonenberg> If you're going to go the FTDI route
<azonenberg> which is easy but aggravating, the chips and driver stacks are buggy
<azonenberg> Not that there's currently a better alternative
<cr1901_modern> azonenberg: I don't need JTAG. I'm trying to keep components as simple as possible for now, and FT232H is more complicated than FT245
<azonenberg> How is it more complex?
<azonenberg> usb pins, data pins, some decoupling caps
<azonenberg> jtag will, if nothing else, give you better diagnostics of boot failures
<azonenberg> I'm not recommending it over the 245 necessarily, but you should make a well-thought-out decision
<azonenberg> Which means having a good reason
<cr1901_modern> azonenberg: The idea was to also use a cheaper chip. I can reuse pins between programming and running if I don't bother adding JTAG. However, I believe JTAG pins are single purpose; so if I use some of the FT232H pins for MPSSE, I lose access to them after the FPGA starts running
<azonenberg> Not true
<azonenberg> With xilinx, at least
<azonenberg> The pins can still only be used as jtag, but there is support for custom jtag instructions that go to fpga fabric
<cr1901_modern> Then I can't use queue mode. So then I need FT2232H which is even more expensive
<azonenberg> what do you mean? Just set IR to USER1
<azonenberg> jump to SHIFT-DR
<azonenberg> and start clocking data in serial just like you would with SPI
<azonenberg> every 8/32 clocks, process the word
<azonenberg> i actually put an ethernet-esque framing protocol inside jtag for antikernel packetized data to use as a runtime debug bridge
<azonenberg> But that is overkill for most stuff
<cr1901_modern> Oh, I'm fairly set on using FT245 queue mode after the FPGA starts running
<azonenberg> ah, ok
<azonenberg> also is the marginal cost of the 2232 vs the 232 significant compared to the FPGA?
<azonenberg> I guess it depends on the choice of FPGA
<cr1901_modern> It wouldn't make much of a difference from my laptop's POV thanks to MPSSE
<azonenberg> i'm used to doing designs with $100+ chips where if i can spend an extra $2 to make the board easier to debug it's totally worth it
<cr1901_modern> but the h/w on the FPGA it makes things easier if it sees a queue
<azonenberg> For a high volume low-budget design, different story
<cr1901_modern> This is a low-volume, low-budget design
<azonenberg> My protocol over JTAG has a TCP socket at one end and the layer-2 packet protocol for antikernel at the other
<azonenberg> As a minimum, if you go with the 245 instead
<azonenberg> I strongly suggest you pin out jtag to a debug header in case you need it
<rqou> right, this discussion reminds me that i really should get to work on programming some cheap cortex m0 to do jtag+uart+fifo+etc. misc. control
<cr1901_modern> azonenberg: THAT was in my plan
<cr1901_modern> :P
<cr1901_modern> azonenberg: The cost is enough to bug me, considering the FPGA is $5, and FT2232H is $2 more
<azonenberg> $5 FPGA? yeah the cost is a significant issue
<azonenberg> If you're using an xc7a200t? NOt so much
<azonenberg> Not*
<azonenberg> rqou: I already have a jtag-over-TCP protocol for the PC-based jtag cable server i wrote
<cr1901_modern> Interestingly enough, FT232H is about the same as FT245RL
<azonenberg> And a mostly finished FPGA implementation of that same protocol using my TCP offload engine
<rqou> i was intending to make it a (hopefully less buggy) ftdi clone
<azonenberg> now see, i wanted to nix usb and go with PoE
<azonenberg> much higher bandwidth and lower latency
<cr1901_modern> PoE is a clusterfuck
<azonenberg> or at minimum, ethernet + barrel jack power
<rqou> how about fake PoE?
<cr1901_modern> There's so many design considerations for your PCB to get it to work right that I just couldn't be arsed to learn about it
<azonenberg> rqou: ?
<rqou> just applies a dc bias between some of the pairs and doesn't do any negotiation
<azonenberg> That's the only kind of PoE i've worked with to date
<azonenberg> just a passive injector stuck between a non-PoE switch and an IP camera
<azonenberg> Didn't seem too complex from the PCB side
<azonenberg> The other thing is, i need the b/w because i wanted multiple jtag ports
<azonenberg> like, say, ARM + FPGA or something
<azonenberg> or even multiple FPGAs
<azonenberg> Once i have the FPGA and TCP offload, the marginal gate count for adding a couple extra shift registers is nil
<rqou> the real 802.3af has a bunch of power negotiation stuff going on
<cr1901_modern> azonenberg: This may seem hard to believe, but... ICE40 doesn't HAVE JTAG lmfao
<cr1901_modern> *I* can't find any reference to it anyway
<azonenberg> How about 802.3at?
<cr1901_modern> Perhaps I should consider an LX4
<azonenberg> cr1901_modern: I had trouble finding it for microsemi
<azonenberg> Don't know what the deal w/ lattice is
<rqou> wikipedia[citation needed] says that all of the real PoE have wattage negotiation
<azonenberg> I know that UG380 has the docs for jtag on spartan6
<cr1901_modern> Well I could ask clifford if he'd ever log back on
<azonenberg> rqou: yes but you have to apply power to do the negotiation, no?
<rqou> it's probably something like the usb "initial 100 mA, the negotiate more" logic
<azonenberg> Exactly
<rqou> wikipedia claims that most of the passive injectors are pinout compliant, they just don't do negotiation and always supply max power
<azonenberg> Makes sense
<azonenberg> Which is legal as the negotiation says "I will supply at least this much power"
<azonenberg> not "I will never supply more than this much power"
<azonenberg> So looks like I should be able to make a non-negotiating (and non-compliant) device that just runs off a passive injector, then push a firmware update to do negotiation if the remote end supports it
<azonenberg> and be fine
<rqou> probably
<azonenberg> also looks like one variant of the negotiation is handled by changing a resistor between the pairs during startup?
<rqou> let's be honest, nobody non-enterprise cares about real PoE
<rqou> :P
<azonenberg> Lol
<azonenberg> Well what i mean is, if i design the hardware to be capable of doing real PoE
<rqou> (ironically I have a "real PoE" device in my apartment right now. thanks housemates)
<azonenberg> I can always not implement that part of the firmware if it never proves necessary :p
<azonenberg> I have a fairly high end cisco switch, or at least it was at one point
<azonenberg> 2970G-24TS-something
<azonenberg> no PoE though
<azonenberg> so i got a 6-port passive injector to run my security cameras
<azonenberg> 24x 10/100/gig copper + 4x gig-only SFP
<azonenberg> pretty sure it's EOL'd now though, lol
<azonenberg> I'm planning to replace it with a homebrewed switch if/when i have time to build one
<azonenberg> i dont need most of the cisco fanciness, i just want basic management for things like vlans
<azonenberg> I already implemented a vlan-capable MAC address table IP core in verilog, has the b/w to support 24x 1gig + 2x 10gig uplinks
<rqou> one of my apartment-mates brought in a meraki setup because he used to work there
<rqou> so he was dogfooding
<azonenberg> and i have 10/100/gig baseT and gig SFP cores
<azonenberg> So basically to get a dumb unmanaged switch I just have to write the forwarding fabric itself
<azonenberg> plus, if i want 10gig uplinks, a 10gig SFP controller
<azonenberg> Plus design the PCB, which will be relatively straightforward (though expensive b/c big FPGA and lots of layers)
<rqou> i also have one of those weird Quanta LB48M switches that I haven't set up
<azonenberg> My plan is, XC7A200T-1FFG1156C
<azonenberg> optional QDR-II+ SRAM in case i want more memory for doing layer-3 switching and want bigger buffers or routing tables or something i cant fit in block ram
<azonenberg> TLK10232
<azonenberg> Use 8 of the 16 GTPs as two XAUI links for 10gbit uplinks
<rqou> the Quanta LB48M is 48x 1000base-t and 2x 10g sfp+
<rqou> apparently it's pretty cheap on ebay
<azonenberg> The other 8 GTPs as 1gig SFP interfaces
<azonenberg> Then i have 500 GPIOs, minus what i use for RAM (and a CPU interface if i throw an ARM down on the board for futureproofing)
<rqou> yeah, i remember you showed me your work-in-progress board for this
<azonenberg> to use for as many RGMII PHYs as i feel like dropping down
<azonenberg> Not the same project but will reuse ~95% of the RTL
<azonenberg> That board was the backplane switch card for the FPGA cluster
<azonenberg> I'm talking about a top-of-rack switch based on the same FPGA and switch core
<azonenberg> just a new PCB layout with more physical interfaces and no card edge connector
<azonenberg> In the longer term i want to make a faster version of it as a backbone switch of some sort
<azonenberg> use one of the new ultrascale parts supported by vivado webpack that have like 16 10gig serdes
<azonenberg> have say 12 10g ports and a 40g uplink or something
<azonenberg> or 8 and two 40g's
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<pointfree> okay cool
<pointfree> wrong channel woops
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<pointfree> azonenberg, clifford: I asked bkuhn of the Software Freedom Conservancy in #conservancy about some legal things, then it occured to us that it would be useful for the whole Free/Open Source FPGA ecosystem to join the conservancy as one entity or so.
<pointfree> for it legal (and other) services.
<azonenberg> Well right now this project has no legal existence
<azonenberg> we're not a corporation or anything
<azonenberg> we're a bunch of individuals working on a shared goal
<azonenberg> And i'm in no hurry to change that
<pointfree> I think how it works is the conservancy would serve as the legal entity and provide some legal protection, also subsidizes travel costs for meetups, hackathons etc.
<azonenberg> Well, keep it in the back of your head but not in a rush to do that
<pointfree> any particular reservations/questions about it at the moment?
<pointfree> I figure reverse engineering is something that requires some more legal safety than your typical project.
<azonenberg> Yes
<azonenberg> My greenpak stuff does not really involve much RE and has th evendor's consent
<azonenberg> The coolrunner stuff is silicon RE which is pretty black and white
<azonenberg> The rest i'm less sure of
<pointfree> I'd personally like to hear from the maintainers of the other projects but I don't know all of their irc handles (arachne-pnr, icestorm, yosys, verilator)
<azonenberg> arachne/icestorm/yosys are all related to clifford
<azonenberg> Yosys doesnt do RE, neither does veriloator
<azonenberg> verilator*
<pointfree> right
<pointfree> but if icestorm and openfpga join, the others might as well join for their other services.
<azonenberg> The more plausible option wouuld be for me to form an LLC or something that operates the project
<azonenberg> But again, seems like a hassle we dont need
<pointfree> the Conservancy would handle all the annoying administrivia for us, but as you said there is no hurry to do this. If there are no objections and no one else wants to deal with application I can do it as I would take some comfort in their personal liability protection.
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