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<azonenberg> cr1901_modern: sure, go send it
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<pointfree> Top DSI's: Bank0: DSI4, DSI5, DSI6, DSI7, Bank1: DSI12, DSI13
<pointfree> B0_P0, B0_P1, B0_P2, B0_P3 B1_P2, B1_P3
<pointfree> Bottom DSI's: Bank0: DSI0, DSI1, DSI2, DSI3, Bank1: DSI8, DSI9
<pointfree> B0_P4, B0_P5, B0_P6, B0_P7 B1_P4, B1_P5
<pointfree> (the layout and numbering pattern of the UDB Pairs and DSI blocks in their banks. I hope your IRC client uses a monospaced font, cyrozap)
<cyrozap> pointfree: Nice!
<cyrozap> My client shows it fine, but the channel log stripped out all the extra spaces.
<cyrozap> And it also got the message order mixed up...
<pointfree> Well, here it is on the wiki for easier reading: https://github.com/azonenberg/openfpga/wiki/DSI-Registers
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<azonenberg> So I think i know what has to be done to continue work on the DAC implementation
<azonenberg> but at the rate things are going it probably will not happen until after i get back from my wedding
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<pointfree> cyrozap: the physical arrangement of I/O ports with respect to the DSI blocks makes less logical sense but it is consistent (for input, that is. Inputs are directly connected to a DSI block and their mapping to DSI's is not configured)
<pointfree> that's the next picture to complete.
<pointfree> I'm thinking a lot of the ports are associated with the analog array or various on-chip peripherals.
<pointfree> That might also explain the gaps in numbering between the UDB banks and such.
<pointfree> the bigger package will have more pins. doh!
<azonenberg> :)
<azonenberg> Would not surprise me if a lot of psoc dies are the same but missing bond pads
<azonenberg> greenpak has at least one case where the same die is bonded out two different ways
<azonenberg> same total pin count but you trade one GPIO for a vcc pin to get a separate i/o raio
<azonenberg> rail*
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<pointfree> Yeah, I think that's the case with my CY8CKIT-059 (CY8C5888LTI-LP097) with regards to I/O. All PSoC 5LP's have 24 UDBs etc. Although there are different amounts of flash and ram across the PSoC 5LP family.
<azonenberg> well flash/ram is probably different masks
<azonenberg> because the only reason to have less ram is to save power
<azonenberg> and die size (aka cost90
<azonenberg> )*
<azonenberg> the only reason to have less flash is to reduce die size (i guess it probably saves a little power too, but not as much since it doesnt leak like sram)
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<pointfree> makes sense
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<pointfree> Even in the biggest PSoC 5LP package not all DSI's are associated with an I/O pin port. Updated with presumptive port locations: https://github.com/azonenberg/openfpga/wiki/DSI-Registers
<pointfree> ...but that's actually kinda consistent with Patent US8026739 FIG.11: https://cdn.rawgit.com/wiki/azonenberg/openfpga/images/US08026739-20110927-D00011.png
<pointfree> One of the DSI blocks is connected to the microcontroller.
<pointfree> The remaining two... to nothing(?)
<cyrozap> pointfree: The DSI also connects to the DMA engine, interrupt controller, etc.
<pointfree> cyrozap: ah! right.
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<cr1901_modern> I AM about to say "hell with it" and just use FT2232H, but I'm not happy about it
<cr1901_modern> Lattice DM'ed me. Told me to read the FAQ, then file a tech issue if I can't find the answer
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