11:00 <Orfeil> whitequark: in reference to "cannot find -llog". I am using ubuntu 16.04 64 bit.

19:14 <pointfree> PSoC 5LP flash programming is not yet supported by openocd so I tried to run some NOPs (0xBF00) in SRAM starting at 0x1FFFF000 (SRAM_CODE): "kitprog reset_target; halt; psoc5lp.cpu mwh 0x1FFFF000 0xBF00 100; reg sp 0x1FFFF000; reg pc 0x1FFFF004; resume" ...The pc does not advance. Has anyone had success with this?

21:49 <pointfree> halt; psoc5lp mass_erase 0; flash write_bank 0 demo.bin 0x0; kitprog reset_target

21:50 <pointfree> ^ the openocd patches do in fact support flash programming

21:51 <pointfree> Although it would still be nice load and run images directly into sram during development.

21:56 <pointfree> I've got a blinking blue led from flash resident arm code right now. yay!

22:04 <pointfree> also, cyrozap, if you want to know why the interface nybles are mirrored, look no further than the bundles of interface lines in FIG.16 https://cdn.rawgit.com/wiki/azonenberg/openfpga/images/US08026739-20110927-D00016.png

22:04 <pointfree> The HC bits are connected to the interface lines diagonally by nyble, so you can see why the top and bottom PI Tile nybles are flipped with respect to each other.

22:19 <pointfree> pretty soon I'll be loading configuration from the 0x48000000 non-volatile config storage area at PoR using the arm and I won't need to tether over SWD anymore.

22:30 <whitequark> is that an image from a patent?..

22:36 <pointfree> whitequark: Yes, https://github.com/azonenberg/openfpga/wiki/Patent-US8026739 https://www.google.com/patents/US8026739

22:37 <whitequark> wow, that's a ridiculously detailed and also bizarre thing to patent

22:39 <pointfree> It was also implied to be the only documentation Cypress has on the routing fabric.

22:40 <whitequark> lawyer-driven development?

22:41 <pointfree> hahas

22:42 <pointfree> It is very useful documentation.

22:42 <pointfree> I really like the way the PSoC routing works.

22:43 <pointfree> It works by short-circuiting, making for a lot of connectivity.

22:51 <pointfree> cpld configuration bitstream is more elegant and aesthetically pleasing than any typical register machine cpu I've encountered to date. Although, TTA's are quite pleasing.

23:06 <whitequark> transfer triggered archs?

23:07 <pointfree> yeah

23:18 <cr1901_modern> pointfree: "cpld configuration bitstream is more elegant and aesthetically pleasing than any typical register machine cpu" What do you mean by register machine CPU configuration?

23:18 <cr1901_modern> Also TTAs actually look really cool! I have use for one to drive an old peripheral chip from an FPGA.

23:27 <pointfree> cr1901_modern: by register machine I mean like an ARM or an x86. James Bowman's J1 CPU or an RTX2010 would be stack machines not register machines. I wouldn't quite call belt machines like the Mill CPU register machines either.

23:33 <cr1901_modern> pointfree: Why do you say CPLD configuration bitstreams are more elegant than a register machine? I think I'm confused as to why you're comparing the two.