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<emeb> OK - 50MSPS 14-bit ADC input -> up5k w/ decimating downconverter -> pulse density modulated audio baseband working now. This is with yosys/nextpnr and the -dsp option.
<agg> how much downsampling are you doing? that's a pretty good result!
<emeb> up5k multipliers properly inferred for the IF mixer and FIR filters. Giant CIC adders with long carry chains also properly synthesiszed. Uses about 44% of LCs.
<emeb> It's going from 50MSPS to 24kSPS.
<agg> nice
<emeb> Need to redesign the final 8x decimation FIR to handle higher output sample rates. CIC has programmable decimation of 128/256/512, but the FIR filter only runs at the 512 rate.
<agg> i was doing 400ks/s->200s/s 16bit as 7 FIR stages and just about fit
<agg> CICs presumably help a lot
<emeb> Yeah - CIC is essential for high decimation rates.
<agg> eh, i was decimating by 2000 ok with just fir :p
<agg> can't remember why i was avoiding cics though, i think a mix of not wanting to deal with the frequency response and the fairly long words at 16bit data
<emeb> Once you wrap your brain around them they're pretty easy to do.
<agg> sure, i've implemented them before, just chose to stick with fir for this particular thing
<emeb> Important part here was to split the long adders up & pipeline the carries.
<emeb> up5k is kinda slow
<agg> presumably you're splitting up the adders by hand?
<emeb> It's coded that way, yeah.
<emeb> yosys doesn't handle that automatically.
<emeb> but you're right - CIC frequency response & aliases get a little weird at higher frequency - that's why I follow them with a narrower FIR to clean up the crud.
<agg> yea, i've usually put a /2 fir after a cic, do you also adjust the fir freq response to cancel out the cic?
<agg> is yosys inferring the multiply+accumulate all into the hardware block? i was instantiating the sb_mac16 myself to control its various confusing options
<emeb> Yep - yosys infers the mults correctly from high level RTL.
<emeb> It's not handling the accumulator properly though - it seems to ignore that and pushes it out into the fabric.
<emeb> Could probably reduce utilization & improve timing if it did.
<agg> might just need to tweak the rtl a bit to let it infer the accumulator too, but it wasn't too hard to just use the instance directly i found
<agg> do you have an rf frontend feeding it?
<emeb> I've got an R820T2 board I built a while ago that works with this ADC, but for now I'm just driving it with a signal generator, or with an HF antenna + 20MHz LPF.
<agg> cool
<agg> oh right, i was doing 8 channels at the same time, so only had one mac per channel which was time-shared between the 7x 31tap FIRs per channel, that was part of why it was a struggle to fit
<emeb> Wow. Lots of fun resource sharing there.
<agg> in the end i had one bram with all the fir coefficients and another with all the fir delay lines and basically a mac with 'a' hooked to one bram and 'b' hooked to the other
<agg> and some annoying sequencing to handle which fir was active when and so forth
<emeb> Yup - my FIR is the same. One mult shared by I & Q channels with a 256-tap FIR
<agg> i wanna get an ecp5 and try it out, their macs are a lot smarter
<agg> faster too, but a lot more options for cleverness inside the mac block
<agg> still pretty cool just how much dsp you can fit into an up5k
<emeb> I've got a ULX3s - need to figure out some fun SDR stuff for that too.
<emeb> But this up5k project has been on the back burner too long & needed to see some progress.
<daveshah> The ECP5 MACs are a lot more painful to actually use
<agg> oh boo :p how come?
<daveshah> there is less low level documentation, they kind of assume you will use the Diamond wizards
<emeb> bleh
<agg> that's a pain. the ice40 at least has that one horrible block diagram that shows what every config bit does
<emeb> lol yes. that thing is kinda intimidating.
<agg> even if it turns out you can't just disable _all_ the registers to make it go faster :p
<emeb> haha - learn to love pipelining
<agg> daveshah: it looks like the sysDSP usage guide does still have the hardware primitives and a description of what all the config bits do, though?
<daveshah> Yes it is just quite vague in places
<daveshah> At least the version I looked at
<agg> i could well believe it's missing all the details i'll only be looking for when i actually try to use it
<agg> also it seems like the primitives they describe are multipliers or ALUs but not MACs
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