18:25 <tnt> What are the advantage of pybind vs what's there now ? Also does that change the exposed "API" ?

18:28 <daveshah> There will be no end user change, but it should be easier to build than Boost Python

18:28 <daveshah> And it will be vendored in to the repo so it removes a dependency

18:34 <tnt> ack tx.

18:35 <kc8apf> https://www.bittware.com/fpga/250-m2d/

18:36 <kc8apf> FPGA accelerator boards are getting tiny w/ soo much ram

18:39 <daveshah> Wow that's neat

18:39 <daveshah> Don't think I'd get that heatsink in my laptop though :p

22:41 <emeb> Playing around with the EHXPLLL in ECP5 - trying to figure out what the various parameters mean. Most of them are fairly obvious, but the CLKO*_DIV parameters are kind of cryptic.

22:43 <emeb> I guess they're just more dividers, and if they're inside the loop then they just push the VCO freq around while the output stays constant. Using lower values for these definitely affects the sidebands

22:45 <zyp> emeb, did you read TN1263?

23:00 <emeb> zyp: I've skimmed it.

23:01 <emeb> zyp: here's what I've seen on my analyzer when playing with those values ->https://www.dropbox.com/s/jtkzwli87inh4ao/0723201549.jpg?dl=0

23:02 <miek> emeb: have a look at figure 23 in there

23:02 <emeb> yellow trace is CLKOP_DIV = 15 (VCO = 600MHz), while blue trace is 8 (320MHz - slightly below the suggested 400MHz min)

23:02 <emeb> miek: yes - been staring at that already.