<sorear>
so we have a vaguely sha2-like structure but with a more complicated round function, no message expansion, and no attempt to ensure reversibility
<sorear>
the last one is going to be Bad on long files b/c internal collisions, but it seems like you're limited to 4kb
<sorear>
data dependent rotations, too
<sorear>
the lack of message expansion probably means this is a great target for differential
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<Stary>
ooh custom n64 bootcode could be interesting, afaik one of the toolchains currently just ships the 6102 version and the other asks you to get it
<Stary>
i've been poking at a n64 cart emulator w/ ice40 for the past couple months or so as a way to get to grips with fpga stuff properly
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<azonenberg>
daveshah, lain, etc: so re the 130nm efabless skywater etc stuff
<azonenberg>
Who's interested in putting together a team to design a true open FPGA?
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<lain>
I'm not sure how much I could contribute, but count me in
<sorear>
how much scary analog / custom layout is that?
<whitequark>
azonenberg: i could probably do yosys and nmigen
<pie_>
:O
<azonenberg>
whitequark: my thought was to do the actual fpga core in systemverilog, but i'd have no objection to nmigen support for user designs
<azonenberg>
i think the first step would be to do a bit more research on e.g. what sram macros and such will be available
<whitequark>
azonenberg: yeah that was the idea, i won't have time to work on the core
<azonenberg>
ah ok
<whitequark>
but i can provide tooling most likely
<azonenberg>
yeah i wanted to do the core myself but i will need help with tooling
<azonenberg>
also, input from tooling developers on architecture
<azonenberg>
i'm a firm believer in hw-sw codesign
<azonenberg>
design the hardware for the software that has to interface with it, and vice versa
<azonenberg>
i.e. the antithesis of intel's approach :p
<azonenberg>
My thought is to target a soc application that has an fpga plus a risc-v core
<azonenberg>
the riscv will have some dedicated SRAM and boot off an attached spi flash, the fpga will boot off a second spi flash. Both are completely independent and you can use the fpga without the cpu and vice versa
<azonenberg>
however the cpu will have minimal peripherals other than the fpga
<azonenberg>
i want to avoid falling into the trap of zynq where the fpga is just a peripheral for the cpu and is a pain to use solo
<azonenberg>
i want an fpga with an attached processor
<mwk>
heh
<azonenberg>
probably no hardware multipliers, this isn't going to be too useful for heavy DSP
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<azonenberg>
block ram is a must, 1-2 plls if there's an open IP available
<mwk>
as of ultrascale, zynq can be used without the cpu, and it's called kintex :p
<azonenberg>
if not, just run directly off external clocks
<azonenberg>
mwk: lol
<mwk>
(srsly they use the same dies)
<azonenberg>
wait what?
<azonenberg>
kintex ultrascale is a zu with the cpu disabled?
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<mwk>
kintex ultrascale+, except for xcku3p and xcku5p, is zynq with disabled cpu
<azonenberg>
wooow
<sorear>
you don't want to try to yolo a pll? :p
<azonenberg>
sorear: i was actually thinking a DLL might be easy enough to yolo in pure digital logic
<azonenberg>
like a spartan6 DCM
<sorear>
you mean a DPLL?
<azonenberg>
its a jitter machine, but usable for some level of clock synthesis
<azonenberg>
mwk: do they at least have extra gpios to pin out?
<azonenberg>
rather than having all of the MIO pins just be NC balls?
<mwk>
yeah, the packages are different
<azonenberg>
sorear: i mean a pll where the oscillator is a tunable ring oscillator
<azonenberg>
i.e. a variable tap delay line plus an inverter
<azonenberg>
anyway, i think we need to wait another few weeks before we make any decisions about architecture etc
<azonenberg>
because we dont have enough info
<azonenberg>
the pdk isnt fully released, we don't have details on ram compilers etc
<azonenberg>
or even how fast the io cells are
<sorear>
oh that's something I hadn't considered
<azonenberg>
sorear: that's what a DCM is
<azonenberg>
it effectively DDS's the target frequency by jittering between taps above and below
<azonenberg>
because it's constantly a little too fast or slow
<azonenberg>
the long term trend can be very close but short term there's a lot of jitter
<sorear>
was thinking of the classic current-starved ring oscillator PLL versus. a PLL where the ring oscillator is implemented with conditional inverters in parallel so that the drive strength, and thus delay, can be digitally tuned
<azonenberg>
period of a DCM output clock after some smoothing to clean up sampling noise
<azonenberg>
you can see it's a bimodal distribution
<azonenberg>
... which is also modulated by power supply voltage as seen in the bottom graph, this board had some power integrity problems. But that's besides the point
<azonenberg>
it's possible they use drive strength tuning but i think it's a delay line
<azonenberg>
at least that's how i'd build one
<mwk>
azonenberg: btw I wouldn't be surprised if the 7-series zynq were actually usable as standalone FPGAs; the dedicated FPGA config pins are there, just disguised as RSVD (but the mapping is pretty obvious when you look at bsdl files, they're in the same scan chain positions)
<azonenberg>
Yeah
<azonenberg>
I've thought about trying it at some point but havent bothered to spin a board. no point when you can just buy an artix
<mwk>
right
<sorear>
do the kintexes have gpus?
<azonenberg>
sorear: the zynq ultrascale+ have some models with a basic gpu iirc
<mwk>
disabled along with the cpu, yea
<azonenberg>
its nothing fancy
<azonenberg>
mali 400 or something like that
<mwk>
standard-issue mali, yes
<sorear>
azonenberg: yeah I just looked up the product table and I'm wondering which corresponds to kintex
<azonenberg>
mwk: But basically what i want to build is something between a psoc and a zynq
<miek>
mithro: i got Unable to checkout 'cb9c90b1f0193ea950c2a49c5e85df1c04deb252' in submodule path 'libraries/sky130_fd_sc_hd/v0.0.1' - everything else checked out ok