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<implr>
when outputing synth netlists via write_verilog, vivado will sometimes generate module *declarations* with stuff like: .\sendCompCount_reg[0] (sendCompCount_reg_0__s_net_1),
<implr>
(declaration, not instantiation)
<implr>
yosys doesn't accept that, syntax error
<implr>
what is that thing?
<implr>
I can't find any reference to what this does
<ZirconiumX>
implr: ".\" or "\"?
<implr>
.\
<implr>
the escape is not the problem here
<ZirconiumX>
Since \sendCompCount_reg[0] looks like a Verilog raw identifier
<implr>
yep, that is fine and works
<ZirconiumX>
Which Yosys sometimes generates when emitting a memory in flops
<implr>
another example: .TRACE_DATA({\TRACE_DATA_PIPE[0] [1],\TRACE_DATA_PIPE[0] [0]}),
<ZirconiumX>
Wait
<ZirconiumX>
Can you send the entire section?
<implr>
uh, I can send you the entire file, but it's like 15M
<implr>
sec
<ZirconiumX>
Not the entire file
<implr>
the section is tens of thousands of lines anyway
<ZirconiumX>
<implr> another example: .TRACE_DATA({\TRACE_DATA_PIPE[0] [1],\TRACE_DATA_PIPE[0] [0]}), <--- this is raw identifier syntax