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<whitequark> azonenberg: one thing i agree with you is annoying about yosys is the immense proliferation of custom attributes that are unscoped
<whitequark> some of them are sort of like the synplify ones but subtly incompatible
<whitequark> i've had this idea of making an "attribute map" or something that could let yosys pretend to be different frontends, but it's hard
<azonenberg> Yes. I don't care what attributes are used internally
<azonenberg> but i want to be able to take rtl built for vivado or something else and run it on yosys
<azonenberg> this also extends to, for example, reading xilinx SDC constraints into nextpnr down the road
<whitequark> nextpnr normally reads vendor constraint files, actually
<whitequark> already does
<azonenberg> Nice
<whitequark> i'm not sure about xilinx sdc but i'll volunteer to implement it if no one else does
<whitequark> i mean once it has xilinx support
<azonenberg> basically i have no objection to improving on the vendor's interface via e.g. a better constraint format or something
<azonenberg> iff we also support the vendor format, either simultaneously or via an argument to select the mode to use
<azonenberg> this goes for constraints as well as rtl
<whitequark> so, this is not really how yosys is currently built
<whitequark> i've added support for exact vendor attributes in a few places
<whitequark> for example, on ice40 and ecp5 you can now use synplify attributes to decide what you want to use to implement BRAM
<whitequark> well
<whitequark> to implement RAM. BRAM, FFRAM, LUTRAM
<azonenberg> Do you support the xilinx ram_style attribute yet?
<azonenberg> if not i'd like it at some point. not a priority until systemverilog support improves
<azonenberg> because i cannot use current yosys with my projects until enums and structs work
<azonenberg> and last time i checked those weren't supported
<whitequark> I added the infra for ram_style attributes
<daveshah> They are both supported to some extent now, I saw a PR for structs was merged recently
<whitequark> you cna probably copy the ECP5 ones with minor modifications
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<whitequark> I don't work with Xilinx so I didn't add the actual values for Xilinx
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<azonenberg> daveshah: ooh i'll have to try
<azonenberg> i dont actually have any ecp5 devkits, i should grab one at some point and see how far things have come
<daveshah> haven't tried them myself yet so can't comment on completeness
<azonenberg> i'd love to be able to do formal on my code again
<azonenberg> i stopped doing formal once i moved to SV
<azonenberg> the productivity gains of SV outweighed the benefits of formal in the near term
<tnt> daveshah: Did you ever find a variation of the ice40_carry_pack_fixes branch that fixed the issue without introducing other issues ?
<daveshah> No, I need to rewrite the iCE40 carry code as it is a mess but I haven't got round to that yet
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