<mithro>
pie_: They released (most of) the UniSim library under an Apache 2.0 license and posted it on github
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<mithro>
"The request for the Xilinx Unisim Library to be published as open source <has been completed and it> has been hosted on GitHub with the Apache 2.0 license here: https://github.com/Xilinx/XilinxUnisimLibrary -- The repo is marked as ‘archived’, but it obviously can be forked for further development by the community. "
<Finde>
that is really cool
<Finde>
wouldn't have expected it from them
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<Finde>
could someone realistically use this to make a compat library for other FPGAs? having trouble thinking about the IP implications
<daveshah>
The PLL and MMCM models do seem to be open source
<daveshah>
An ideal PLL isn't too hard to model
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<ZipCPU>
Properly modeling a PLL requires differential equations. It's commonly done with Laplace transforms. Properly modeling a discrete time PLL requires using difference equations with semantics very similar to differential equations. That's why my article skipped that part. A proper model would've been able to (roughly) predict the performance seen in my article.
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<nats`>
ZipCPU, IIRC it's true for the steady state PLL
<nats`>
but the modeling of the transient part is way more complicated
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<emeb>
Heh - I wrote a behavioral model for a PLL in verilog on the day job about 20yrs ago. That was a hoot.
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<azonenberg>
emeb: i have a generic behavioral pll model too that i wrote for some tests a while back
<azonenberg>
but it's not intended specifically to model the behavior of any particular real hardware
<emeb>
azonenberg: yeah - mine was very simple. modeling the VCO with just simple delays, loop filter was completely wrong, etc.
<azonenberg>
i had no loop filter :p
<azonenberg>
it was a pure clock synthesis block that locked instantly to the Nth harmonic of the incoming signal
<azonenberg>
I also have made a much more complex pll i use in libscopehal for clock recovery
<azonenberg>
which is an actual real CDR PLL, although the loop filter is a somewhat arbitrary bang-bang controller rather than trying to model anything specific
<azonenberg>
i want to implement the fibre channel golden PLL at some point
<azonenberg>
but don't yet have the background to understand it :p