21:18 <tnt> Damn, the S3 is frustrating ... the logic cell allows some nice tricks, the ram is pretty flexible too ... but it's just _SO_ slow that it's pretty much useless for anything I can think of.

21:20 <nats`> it's old

21:20 <tnt> old ?!?

21:20 <tnt> QuickLogic EOS-S3 ... not Xilinx Spartant 3

21:29 <zyp> I want to run my own usb core on it, which I hope it will be fast enough to do, since it ships with demo code doing usb

21:30 <zyp> although the demo code seems buggy, it doesn't enumerate properly here

21:31 <tnt> zyp: porting my usb core was what I was trying to do.

21:32 <zyp> do you know which core is used for the demo code? it has the tinyfpga PID

21:33 <tnt> It's a heavily modified version of the tinyfpga bootloader ... with lots of added pipelining and manual cell instanciation and manual cell placement and run through their closed p&r tool to make it run at that frequency ...

21:34 <zyp> ah

21:35 <tnt> Given the inter-packet gap of the default tinyfpga botloader is already way above spec, I wouldn't be surprised if all the pipelining added even more delay and they're now over what some hosts will tolerate.

21:36 <nats`> ahhhh I was thinking spartan 3 :D

21:36 <zyp> the issue with enumeration here is that it doesn't seem to reset the address on bus resets

21:37 <tnt> Pretty sure a spartan 3 is way faster than the EOS-S3 :p

21:37 <zyp> and macos for some reason starts with set_address and then resets the bus

21:37 <tnt> zyp: ah oki, possible. I didn't dig tbh.

21:38 <zyp> https://bin.jvnv.net/file/q89fb.png <- it takes the first set_address and ignores the second, and doesn't progress from there

21:40 <zyp> it managed to enumerate with a different host that does a different enumeration sequence though, so I figure it's just not very tested

21:41 <zyp> also, is the power on reset of the chip not functional?

21:41 <zyp> I find I have to push the reset button after powerup to get anything to work, regardless of jumper settings

21:42 <tnt> Huh .. not sure, I've always booted it up with a jtag probe attached which breaks on boot anyway.

21:43 <zyp> I couldn't even get that to attach before pushing the reset button

21:45 <tnt> I know I've had issues ... didn't really bother investigating, once I got it to run and load sw from the probe, that was good enough.

21:51 <zyp> I figured I'd start by getting comfortable with the ARM side, I figure there's not much point to a hybrid mcu+fpga unless both sides are useful

21:53 <zyp> (and I have a lot more cortex-m experience than fpga experience too)

21:54 <tnt> Yeah, I figured that both nice needed to be useful, but I thought that I could trust the cortex-m4 side to be fine and I wanted to check if I could do anything with the fpga first :p

21:56 <zyp> also, you made me less confident that my usb core is gonna fit :p