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<mithro> tnt: If vpr is taking 12 minutes for you, something is going very wrong -- is should take O(30 seconds)
<mithro> whitequark: vpr is currently significantly slower than nextpnr but we are working on improving that
<mithro> It's much worse for smaller devices like EOS S3
<whitequark> okay, sounds good then!
<whitequark> I don't care a whole lot about the exact tech powering a toolchain as long as it's not a PITA to use (build, package, too)
<mithro> vpr takes O(10m) to PnR a LiteX DDR with Ethernet on Artix 7 50T
<mithro> The work on https://github.com/SymbiFlow/fpga-tool-perf and https://j.mp/fpga-tool-perf-spec is designed to help drive more performance improvements
<mithro> Finding contractors to work on nextpnr related stuff is also very hard -- daveshah only has so much time to go around
<whitequark> can other people contribute to nextpnr? why not?
<mwk> ... hmm, I thought there was some company that has people with experience working on nextpnr
<whitequark> also that
<whitequark> if i didn't have my hands full i'd totally consider working on nextpnr
<whitequark> i mean i'll work on nextpnr, just not on an architecture
<mithro> Yes there is, but business to business relationships are complicated
<whitequark> then fund these people as individuals
<whitequark> anyway, as long as the result is good it doesn't matter very much
<whitequark> my concern here is along the lines of "if I can't easily cross-compile the toolchain I wouldn't bother using it in any place where I currently use nextpnr"
<mithro> The best part of the quicklogic stuff is they released the low level data needed to create a toolchain -- https://github.com/QuickLogic-Corp/EOS-S3
<whitequark> the point of having a FOSS toolchain, for me, is it being head and shoulders above the proprietary ones, not being basically as much pain to use but OSS
<whitequark> nextpnr is so fast glasgow doesn't cache bitstreams! *that* is being head and shoulders above
<mithro> nextpnr is certainly super impressive and like llvm made gcc better it is most certainly making VPR think about things like that
<mithro> Did I ever link the proof of concept paper at http://ic.ese.upenn.edu/abstracts/prflow_fpt2019.html
<whitequark> interesting
<mithro> Impact: Able to achieve 12-18 minutes using Vivado -- Contrast 42-160 minutes no PRflow -- Plausible to achieve 2-5 minutes with open source Symbiflow
<mithro> I actually /think/ that was the first academic paper to reference symbiflow and kind of came out of nowhere
<mithro> The VTR 8 paper is actually a pretty interesting read - https://www.eecg.utoronto.ca/~kmurray/vtr/vtr8_trets.pdf -- it talks a lot about comparison to Quartus and Vivado
<mithro> I also do try and send funding in nextpnr's direction -- https://youtu.be/EHePto95qoE?t=689
<whitequark> nice
<mithro> From the VtR 8 paper
<mithro> > First considering the VPR 8 and VPR 7+ timing-driven routers (Timing + WL), we observe the VPR 8 router is substantially more run-time efficient (6.2× faster) while also improving QoR (18% wirelength and 16% critical path delay reductions).
<mithro> > From a run-time perspective, VPR 8 HE runs 1.2× faster than Quartus and has a 4% smaller memory footprint. VPR 8’s packer runs 18% slower than Quartus’, but is much more general purpose. For these large benchmarks, placement dominates run-time (78% of total time), and VPR 8’s placer run-time is comparable to Quartus. The VPR 8 router is more efficient and runs 2.9× faster than Quartus even in this high effort
<mithro> mode. Compared to VPR 8, Quartus spends approximately 3.3× more run-time on STA.
<mithro> The largest benchmark in VPR 1.8 million LUTs too
<mithro> Still lots of work to do
<mithro> Only so many hours in the day
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<mithro> Interesting footprint -- "WLCSP optimized for budget-constrained two-layer PCB designs" -- https://www.nordicsemi.com/News/2020/06/Nordic-nRF52805-adds-Bluetooth-5-2-SoC-in-WLCSP-to-proven-nRF52-Series
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<TD-Linux> in particular there's some shenanigans with the central gnd balls
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<tnt> That PDF only has 343 pages ...
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<tnt> mithro: well, it's possible something is wrong but I would have no clue where to even begin looking ... the bitstream it generate work but the 'route' phase takes forever.
<tnt> My laptop is by no mean recent ( i7-4600U dual core 2GHz ) but building a full soc with usb filling up 80% of a up5k is in the 2m total build time on ice40. A trivial 400 LC design driving a mipi screen takes 3s.
<tnt> whitequark: it'd still be good to have bitstream caching :p When you constantly swtich between two applets, it's a pain even if it only take 10-20s ... (and yeah I know I can manually 'cache' it)
<daveshah> I think there is something in VPR called lookahead that needs to be set up correctly or routing is terrible
<daveshah> idk how it is set up or if that js actually the problem though
<whitequark> tnt: yeah that will happen sometime
<tnt> daveshah: at least in the log there is a "# Computing router lookahead map took 32.86 seconds (max_rss 622.5 MiB, delta_rss +0.0 MiB)"
<daveshah> I think for the Xilinx arches this is computed during build
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<tnt> Anyone know if Olof Kindgren hangs around here ?
<daveshah> Probably you would have more luck on the librecores gitter
<tnt> There is a librecores gitter ? ... -ETOOMANYPLATFORMS :/
<daveshah> Yes
<tnt> But tx :)
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<mithro> tnt: upload an example and people can look into it
<mithro> Great!
<mithro> I'm sure the QL people are feeling a bit overwhelmed at the moment
<Lofty> I spoke to them yesterday
<mithro> Transitioning from a closed to open mindset is a slow and painful process for companies
<mithro> I did warn them that the open source community would pull everything apart and put it back together in weird ways they had never seen before
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<simeonm> Is this a good place to ask questions about Verilator?
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