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<
_whitenotifier-f >
[libfx2] whitequark commented on pull request #4: Add standalone url field to fx2 setup.py -
https://git.io/JfXAC
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<
_whitenotifier-f >
[libfx2] artizirk commented on pull request #4: Add standalone url field to fx2 setup.py -
https://git.io/Jf1UB
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<
tnt >
Anyone managed to build the quicklogic toolchain ?
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<
tnt >
"Installing: /opt/openfpga/bin/liblog.a" ... sriously vtr ... who installs .a into bin now ...
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<
tnt >
Also "liblog.a" ... way to pollute the global namespace with super generic terms.
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<
OmniMancer1 >
tnt: vtr does
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<
tnt >
OmniMancer1: yeah, obviously ...
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<
azonenberg >
Hey daveshah / other lattice folks: any estimates on the power envelope for an ecp5 with a single 1.25 Gbps SERDES lane active and some minimal processing?
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<
azonenberg >
looks like 43 mA VCCA, 13 mA VCCHTX per lane. Hmmmm this is looking feasible
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<
azonenberg >
then 77 mA on vdd plus however much logic uses...
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<
awygle >
whatcha doin zonenberg