##openfpga on 2020-06-02 — irc logs at freenode.irclog.whitequark.org

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03:36 <implr> also, amusingly, see the generated comment at the top

03:36 <implr> >The output is an IEEE 1364-2001 compliant Verilog HDL file

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15:04 <tnt> daveshah: btw, any advice for the SHIFTREG_DIV_MODE patches ? The fact that you need a synchronous change in icestorm and nextpnr is not ideal obviously :/

15:08 <daveshah> Although it's a bit of a hack, it might be have some way of backwards compatible naming for this one so new nextpnr and old icestorm works

15:09 <tnt> I guess is SHIFTREG_DIV_MODE_0 doesn't exist, it could fall back to using the LSB only with SHIFTREG_DIV_MODE

15:10 <daveshah> SGTM

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18:48 <tnt> Damn, the CI builds sure are taking forever ...

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20:40 <_whitenotifier-f> [libfx2] artizirk opened pull request #4: Add standalone url field to fx2 setup.py - https://git.io/JfPLC

20:41 <_whitenotifier-f> [libfx2] Success. The Travis CI build passed - https://travis-ci.org/github/whitequark/libfx2/builds/694011114?utm_source=github_status&utm_medium=notification

20:43 <_whitenotifier-f> [libfx2] whitequark commented on pull request #4: Add standalone url field to fx2 setup.py - https://git.io/JfPLE

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