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<TD-Linux>
is there a convention for addresses for >8 bit wide buses that can optionally be addressed at byte level (via external selects?)
<TD-Linux>
e.g. if I leave in the lowest address bits it makes simulations more readable and gets optimized out anyway, but also is maybe confusing
<tnt>
Some bus have byte select masks that are also valid during read cycles (and not just write masks). They're often just ignored during read ...
<TD-Linux>
yeah that's the case here
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<sorear>
ideally you would support that so that you can interface mmio devices with read side effects without exposing the bus width to software
<tnt>
My take on it is that this often take more logic area than it's worth (in fpga at least, but then this is ##openfpga). So all peripherals have to be accessed with native width access only.
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<TD-Linux>
seems this one wishbone core does output [31:2] ADR_O,
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<tnt>
Can the analytical placer just hang ? Or is it guaranteeds to finish at some point ?
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<daveshah>
It will keep iterating until it stops improving, so in theory this could go on a long time but I've never seen that before
<daveshah>
If it just hangs with no output then it will be the legaliser unable to find a legal placement, although that should have a timeout now
<tnt>
Yeah, it did timeout after about 10m I think.
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<daveshah>
Chances are this is a packer bug
<tnt>
I mean the design is pretty full ( 90% ) but still, I've seen more full :p
<daveshah>
It may be something like getting stuck in a ripup cycle and not being random enough when it comes to control sets
<daveshah>
I think nextpnr needs a control set API so the placer can reason about them better than just trial and error
<tnt>
yeah, I suspect that's the issue. I just added a bunch of 'config' registers on a wishbone bus so that's basically a bunch of FF with different enable lines depending on the address ...
<tnt>
I need to convince yosys not to use DFFE for those.
<daveshah>
Ah yeah Yosys is too good at extracting DFFEs :D
<tnt>
disabling dffe made it go through indeed.
<tnt>
Not ideal because I'd like just to disable those DFFEs ... and not globally.
<tnt>
(because those don't have any logic in front so implementing the enable in the LUT is "free")
<tnt>
I might actually try to implement a python pass for nextpnr detecting such DFFE (with passthrough lut in front) and convert them.
<daveshah>
It's a bit ugly but you could probably write something like (d & en) | (q & ~en) for the problematic code
<daveshah>
I think the xilinx opt_lut pass basically does this
<daveshah>
Or is it something else, I'm sure I saw something added to Yosys like this
<tnt>
I can try that. I tried q <= (en ? d : q); instead of if (en) q <= d; but that hasn't helpers.