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<pepijndevos>
cr1901_modern, over in #apicula david suggested that Gowin clock routing might be similar to xo2, and that you would be the right person to ask how stuff works in xo2.
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<mwk>
... what exactly is the story with ECP5 LUT rams?
<mwk>
I'm looking at TN1264 and it does not really make any fucking sense
<daveshah>
The bottom two SLICEs act as 16x2 RAMs
<daveshah>
The third SLICE feeds through write address and data signals
<mwk>
the timing diagrams for reads are just insane, and there's weird shit like the read address being an *output* in the diagram?
<mwk>
hmmm
<mwk>
so what configurations are possible?
<daveshah>
16x4 async RAM
<mwk>
16×4 SP [SPR16X4C] + 16×4 SDP [DPR16X4C], am I reading this right?
<mwk>
both with completely async reads
<daveshah>
No there is no single port support
<mwk>
ah
<daveshah>
Its always SDP
<mwk>
so the SPR16X4C just happens to have the addresses tied?
<daveshah>
Thats just a compatability primitive
<daveshah>
Yeah
<mwk>
okay that simplifies things
<mwk>
thanks
<mwk>
... well then
<mwk>
I think my yosys memory inference rewrite is design-complete now
<mwk>
time to write it up, I guess
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