<kc8apf>
if you're OK with never being able to hit line rate, you'll need something with a 25G serdes for the ethernet side. USB 3.2 Gen2 needs a 10G serdes so you'd need 2 of those or a UTMI/ULPI transciever
<kc8apf>
sorear: that's more or less what Gen2x2 is. 2 10G lanes
grantsmith has joined ##openfpga
grantsmith has quit [Changing host]
grantsmith has joined ##openfpga
jjeanthom has joined ##openfpga
jjeanthom has quit [Ping timeout: 256 seconds]
<rektide>
kc8apf: usb4 supports 40Gbps transfers. in general my question is, how does one go about getting chips with serdes built?
etrig has quit [Remote host closed the connection]
<kc8apf>
you can either pick an FPGA with fast enough serdes (those won't be small or power efficient devices) or start designing an ASIC and buying IP
<rektide>
something like this? "The DesignWare USB 3.1 SuperSpeed Plus PCS core is a configurable Physical Coding Sublayer (PCS) that
<rektide>
complies with the PIPE 4.3 specification and supports the USB 3.1 SuperSpeed Plus protocol."
<sorear>
a PCS is only part of the stack you need
<rektide>
yeah, that seems to expose a "pipe4" interface, which is where presumably someone needs to be setting up device definitions, & talking over that link
<kc8apf>
Synopsis claims to offer a full USB4 IP stack
<rektide>
ha, ok, so DesignWare has a USB4 PHY IP. which seems to be available for TSMC 5FF @ 1.2V and 6FF at 1.8V, https://is.gd/TPzE3v
<rektide>
oh my gosh, usb4 hubs contain: *a device router, a usb3 & usb2 hub, and.... oh boy... a PCIe switch! also have to support DP tunneling. egads, yikes. from usb.org System Overview, https://is.gd/7vA94Q
<rektide>
i wish usb4 had a 1Gbps mode such that hobbyists could learn & experiment with the new protocol, & ignore all the old versions. not need a 20Gbps link to figure this stuff out over.