s_frit has quit [Remote host closed the connection]
s_frit has joined ##openfpga
jeanthom has joined ##openfpga
X-Scale` has joined ##openfpga
X-Scale has quit [Ping timeout: 240 seconds]
X-Scale` is now known as X-Scale
jeanthom has quit [Ping timeout: 244 seconds]
s_frit has quit [Read error: Connection reset by peer]
s_frit has joined ##openfpga
Lord_Nightmare has quit [Ping timeout: 246 seconds]
emeb has joined ##openfpga
OmniMancer has quit [Quit: Leaving.]
Lord_Nightmare has joined ##openfpga
Lord_Nightmare has quit [Ping timeout: 258 seconds]
<mwk>
ice40 blockram is non-transparent if rclk == wclk, correct? cannot find it in the docs properly...
<mwk>
also, is there any practical difference between re vs rclke or we vs wclke?
<tnt>
the ice40 block ram is non specified if clock the same and you read/write at the same address, read data is undefined.
<tnt>
there is a practical difference between re/we and rclke/wclke. The former is apparently buggy and should be avoided in favor of the latter. That's what icecuble does at least and there as been some report of weirdness with re/we in the github issues.
<mwk>
... lovely
<tnt>
gotta keep things interesting :p
<tnt>
IIRC the re/we only work properly when using the native width (i.e. 16b), but that's ... far back in my memory.