##openfpga on 2021-03-04 — irc logs at freenode.irclog.whitequark.org

00:27 <promach3> keesj: I am coding the DDR3 memory controller in verilog

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06:47 <keesj> promach3: cool

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23:44 * promach3 uploaded an image: image.png (70KiB) < https://matrix.org/_matrix/media/r0/download/matrix.org/GWiivkbXRyYBEPOwAdkxRuKc/image.png >

23:45 <promach3> I am confused with how `TDQS` and `TDQS#` pins be driven ? I suppose these two pins are of `inout` nature

23:47 * promach3 uploaded an image: image.png (59KiB) < https://matrix.org/_matrix/media/r0/download/matrix.org/UVNxuYTeJcBEVcYSofbzXOYC/image.png >

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