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<promach3> keesj: do I really need `tqs` and `odt` ?
<promach3> another question is do I need `twr` for `write_AP` ?
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<promach3> by the way, I had done an initial code for the DDR3 memory controller in verilog : https://gist.github.com/promach/2c477b1dbc39f04a1271fb229e6d678c
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<promach3> sorry should be `tdqs`
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<keesj> promach3: are you doing your own layout or trying to implement a ddr controller? I .. never did either only small projects (like a small up5k based board). https://github.com/gregdavill/OrangeCrab is one of the few open source designs I know of that uses ddr3
<keesj> I also used https://github.com/enjoy-digital/litedram to access the ddr3 memory on the arty (and genrally am working on snooping ddr3 traffic)
<keesj> A.. I see you already looked at the orange crab...
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<keesj> I am very interersted in the topic but don't trust me
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