11:33 <keesj> I created https://git-es.nl.sp/schaapgroup/schaap/-/blob/master/docs/20210226_LAM_specs_v06/EOS-2008C%20LAM%20specification%20v0.6_exset_review_questions.txt

11:33 <keesj> sorry .. off topic..

11:42 <keesj> the intention was to post https://www.eetimes.com/xilinx-opens-up-vitis-hls-tool-for-fpgas/

11:46 <keesj> is this indented to convert algorithms into FPGA code ?

16:39 <pie_> I'm finally 2/3rds of the way through reading http://www.lighterra.com/papers/modernmicroprocessors/ . Now I'm wondering where the new AMD stuff fits.

16:40 <pie_> Such an insightful paragraph...

16:40 <pie_> balance between ILP and TLP? Right now, many different approaches are being explored..."

16:40 <pie_> "Now, given that both instruction-level parallelism and thread-level parallelism suffer from diminishing returns (in different ways), and remembering that SMT is essentially a way to convert TLP into ILP, but also remembering that wide superscalar designs scale very non-linearly in terms of chip area (and design complexity, and power usage), the obvious question is where is the sweet spot? How wide should the cores be made to reach a good

18:35 <kc8apf> keesj: Vitis is a C/C++/OpenCL to RTL compiler