00:56 <etrig> https://twitter.com/edgetriggered/status/1370176329149259783

00:58 <tpw_rules> is there newer software that works for those devices?

01:47 <etrig> tpw_rules: possibly, it's way before my time- personally just interested for the sake of archiving as much as possible

01:48 <etrig> intel also removed all the quartus releases before 13.1

01:48 <etrig> except a few months earlier, before I noticed...

02:27 <pie_> put it on some bootleg archive.org

14:58 <Sprite_tm> Lo all. Got some issue in my FPGA design I need to debug. Is there an easy way to bring out a signal from deep in the Verilog hierarchy out to a GPIO easily, or do I need to add a debug output to all the modules in the middle?

14:59 <Sprite_tm> ECP5, Yosys and Nextpnr based flow, if it matters.

15:00 <whitequark> look into `hierconn` attribute

15:01 <Sprite_tm> Pfff, threw it into google, first hit is one of your tweets :P

15:01 <whitequark> the README explains how to use it i think

15:01 <whitequark> yosys readme

15:02 <Sprite_tm> Readme says 'Wires marked with the hierconn attribute are connected to wires with the same name (format cell_name.identifier) when they are imported from sub-modules by flatten.'

15:06 <Sprite_tm> Am I right that I can just do 'assign my_debug_wire = module.submodule.subsubmodule.some_signal;'?

15:06 <whitequark> this used to not work

15:06 <whitequark> i think there was some very recent work to implement it? try it

15:08 <Sprite_tm> No dice... ERROR: Identifier `\qpi_iface.trans_end' is implicitly declared.

15:08 <Sprite_tm> My yosys is a week or so old, if it matters.

15:08 <whitequark> yeah, try hierconn instead

15:10 <Sprite_tm> Can you help me out with how that would work? I can't seem to find an example anywhere...

15:13 <Sprite_tm> Think I have it... I'm getting an error but that may be because the bug I'm trying to debug. Does this look OK?

15:13 <Sprite_tm> wire trans_end;

15:14 <Sprite_tm> Ugh, I can't copy/paste code.

15:14 <Sprite_tm> wire trans_end;

15:14 <Sprite_tm> // synthesis attribute hierconn trans_end "qpi_iface.trans_end";

15:15 <Sprite_tm> assign IO[0]=trans_end;

15:17 <tnt> Sprite_tm: https://github.com/YosysHQ/yosys/issues/647 no dot notation.

15:21 <Sprite_tm> Looks like it... can't get that hierconn attrib to work either.

15:26 <gatecat> Try using Verilog 2001 syntax: (* hierconn="qpi_iface trans_end" *)

15:26 <gatecat> I don't think Yosys supports hot comment attributes

15:28 <Sprite_tm> That doesn't make it happy either... top_fpga.v:239: ERROR: syntax error, unexpected TOK_ASSIGN

15:28 <Sprite_tm> Ah wait, I think I'm using that wrong...

15:29 <gatecat> oh yeah, it goes on the wire, and I don't think you need the assign at all

15:34 <Sprite_tm> gatecat: something like this: (* hierconn="top_fpga clk100m" *) wire dbg0; ?

15:34 <gatecat> I think so, yeah

15:34 <gatecat> I've never actually used this though, tbh

15:34 <Sprite_tm> No worries, I seem to be a bit in no mans land anyway :/

15:35 <Sprite_tm> Kinda unfortunate that there doesn't seem to be an example or testcase for this either.

15:41 <Sprite_tm> Nope, I give up. Back to adding debug outputs to everything...

15:43 <hell__> out of curiosity, is there an equivalent of "printf-based debugging" for FPGA stuff?

15:44 <Sprite_tm> Probably what I'm trying to do :P output a bunch of signals to GPIOs, have an external 'scope to see wtf is going on.

15:44 <Sprite_tm> Plus a quick edit-synth-upload-run loop.

15:44 <Sprite_tm> And yes, I swear I do sim and formal as well :P

15:51 <tnt> when IO (and IO delays) are involved, looking at what's really happenning is often the quickest way.

16:00 <Sprite_tm> Ahrg. Found the error. What idiot wrote the documentation for the ESP32 SPI interface?

16:00 <Sprite_tm> Oh wait, that was me, years back :/

16:00 <hell__> I know the feeling

16:01 <Sprite_tm> Tbh, I get why I fucked up... didn't ask the digital team for enough details. In SPI mode, 1 clock cycle is 1 bit, and the docs and api are perfectly fine then. However, in QPI mode...