<keesj_>
but perhaps I am thinking .. wrong. I want to write tests that will pass/fail
<keesj_>
so yosys formal uses the systemverilog assert and assume, iverilog does not understand assert and verilator requires writing c++ code
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<balrog>
FWIW: the fast analog/digital circuit simulation library used in MAME was just relicensed under the 3-clause BSD license, if it is of use to anyone here
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<pie_>
wow they have an entire analog circuit sim library?
<pie_>
i guess im not entirely surprised
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<balrog>
pie_: yup!
<balrog>
optimized for speed over accuracy, for playable games
<balrog>
it's used for pong, as well as various audio implementations and other stuff