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<keesj_> I want to fully automate my tests (not view them in gtkwave)..it there an assert keyword or similar?
<keesj_> (verlog/iverilog/yosys)
<keesj_> (verilog/iverilog/yosys)
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<q3k> keesj_: yosys' formal verification would let you do that
<q3k> not sure what about standard testbenches
<q3k> you can probably roll your own assertions that $display("ERROR") and $finish
<q3k> and then just grep around for that
<tnt> There is $fatal too to set exit code to non-zero
<q3k> oh yeah.
<keesj_> so going for something like https://stackoverflow.com/questions/13904794/assert-statement-in-verilog ( the macro as second answer) would be acceptable?
<keesj_> but perhaps I am thinking .. wrong. I want to write tests that will pass/fail
<keesj_> so yosys formal uses the systemverilog assert and assume, iverilog does not understand assert and verilator requires writing c++ code
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<balrog> FWIW: the fast analog/digital circuit simulation library used in MAME was just relicensed under the 3-clause BSD license, if it is of use to anyone here
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<pie_> wow they have an entire analog circuit sim library?
<pie_> i guess im not entirely surprised
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<balrog> pie_: yup!
<balrog> optimized for speed over accuracy, for playable games
<balrog> it's used for pong, as well as various audio implementations and other stuff
<balrog> it presently lives in https://github.com/mamedev/mame/tree/master/src/lib/netlist — and can already be used standalone
<tnt> mame will soon reach sentience ...
<pie_> but first, an email client and a lisp implementation
<balrog> pie_: incorporating a game engine to simulate electromechanical games is more likely.
<balrog> if you're talking about things that seem crazy
<pie_> soo....email client on bar logic?
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