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<whitequark>
tnt: hey, looking at spy-bi-wire
<whitequark>
I'm curious, does the MSP430F1612 on the devkit have the JTAG fuse blown?
<tnt>
whitequark: oh nice:) Did you get one of those launchpad ?
<whitequark>
all DRs appear to be BYPASS
<whitequark>
yes... via some unusually shady means
<tnt>
You mean the msp that's used as the 'programmer' ? No idea, I never looked at it, but that wouldn't surprise me.
<whitequark>
that seems overly paranoid
<whitequark>
I'm wondering if I'm just driving it wrong
<whitequark>
it looks like there's no IDCODE register even
<whitequark>
hm, right, it *doesn't* have an IDCODE
<whitequark>
what a strange chip
<tnt>
yeah, seems a bit paranoid especially since you can download firmware updates for it :/
<whitequark>
I might be still not driving it correctly
<whitequark>
it has some weird "fuse check sequence"
<tnt>
Ah yea, they can have a 'password' IIRC.
<whitequark>
no, different thing
<whitequark>
a fuse check sequence is some weird sequence on TMS/TDI that you need to clock in so that it actually recognizes the fuse is blown (or not)
<whitequark>
and it can fail, with the chip misinterpreting an intact fuse as blown
<whitequark>
shit design imo
<tnt>
wtf
<whitequark>
i couldn't get 4-wire JTAG to work on the DUT either.
<whitequark>
not really a fan of msp430 now
<tnt>
which target device is it ?
<tnt>
I've never actually used 4 wire jtag on any msp430 tbh, I only ever used the 2 wire mode.
<whitequark>
M430G2553
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<tnt>
mmm, you need to enable it somehow ? switch it to 4w mode ?
<whitequark>
I think I am switching it
<whitequark>
but it doesn't work
<whitequark>
shrug
<tnt>
Ah yeah, that's what the 'TEST' pin is for apparently.
<whitequark>
yeah
<whitequark>
i really don't like this chip :/
<whitequark>
ah well
<tnt>
I never had any issues with them, but I always used the official TI FET :p
<whitequark>
though the way i drive TEST is a bit hacky
<whitequark>
so that might still be the reason, yes
<whitequark>
bottom line: i couldn't make it work yet
<whitequark>
tnt: that said... SBW fits really well as an extension of the JTAG applet
<whitequark>
with some small modifications that I might reuse if I ever get around to adding RTCK support
<gregdavill>
I have one of the MSP430-FETs So I could try poking at some MSP430 chips in JTAG mode and give you some logic dumps.
<whitequark>
it's probably fine for now
<tnt>
whitequark: yeah, having a quick look at it when I opened the issue and it seemed it was really jus tserializing the normal jtag, so I figured it'd just be a layer above the normal jtag applet that just simulated its io buffer.
<whitequark>
more or less... clocking adds some complexoty
<whitequark>
complexity*
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<marcan>
whitequark: msp430 is hilarious
<marcan>
it can only be used as the first device in a chain
<marcan>
because it requires a clock on TDI to program
<marcan>
yes on TDI
<marcan>
(which isn't passed through combinatorially through a chain)
* marcan
wrote an msp430 programmer thing in a past life
<marcan>
I should have a FET and some chips lying around
<whitequark>
marcan: yes, i noticed that
<whitequark>
it looks like they fixed it in later chips?
<whitequark>
... sort of
<marcan>
oh they finally have an internal clock now?
<whitequark>
it looks like they do, but i haven't read very closely into it
<whitequark>
their jtag still seems hilaribad
<marcan>
yup
<marcan>
IIRC you program them by streaming instructions into their CPU core
<whitequark>
oh, so like MIPS
<whitequark>
great.
<whitequark>
i fucking *hate* that.
<whitequark>
it's also extremely slow with glasgow cuz of all the USB roundtrips.
<whitequark>
this is why i designed boneless, to stick a core that would generate all of that shite on the FPGA
<marcan>
can't just use a dumb state machine?
<whitequark>
they get *huuuuge8
<marcan>
when I wrote all this shit one of the things I had was a protocol where you could do things like "AND/OR/XOR reg, wait for bit" and just stream that crap via USB
<whitequark>
especially given that yosys' frontend is kind of shit
<marcan>
so I'd avoid the round trips
<whitequark>
that's half a cpu already
<marcan>
yeah, but streaming
<marcan>
so no real loops
<marcan>
just self contained waits
<whitequark>
that's why i said *half*
<marcan>
:p
<whitequark>
and you want something more complex for MIPS anyway
<whitequark>
or probably for *debug* of msp430
<whitequark>
since you want to load all the registers and so on
<marcan>
fun fact: I wrote that state machine to speed that POS up on my last day at that company
<marcan>
(it was a summer job)
<marcan>
(first job too)
<whitequark>
ha
<whitequark>
hm, looks like i refactored the JTAG applet sufficient
<whitequark>
ly. let's try it on a router
<whitequark>
I: g.applet.debug.mips: found CPU with IMPCODE=0x00800904
<whitequark>
I: g.applet.debug.mips: found MIPS32 CPU 0x82 (EJTAG version 1.x/2.0)
<whitequark>
W: g.applet.debug.mips: found cursed EJTAG 1.x/2.0 CPU, using undocumented DCR.MP bit to enable PrAcc
<whitequark>
I: g.applet.debug.mips: target is a MIPS32 R1 big endian CPU with standard TLB MMU
<whitequark>
yep gonna say it works
<_whitenotifier-3>
[GlasgowEmbedded/Glasgow] whitequark pushed 1 commit to master [+0/-0/±2] https://git.io/fj9G2
<_whitenotifier-3>
[GlasgowEmbedded/Glasgow] whitequark b88b7b1 - applet.interface.jtag_probe: refactor to support other transports.