06:12 <ar> kc8apf: i've had a phone that used this - Jolla with the keyboard from a kickstarter

09:17 <eddyb> kc8apf: has anyone documented any particular modern laptop/mobile device, with all of its cores and maybe dumped firmware?

09:19 <eddyb> it'd be cool to build maps, effectively network maps, of all the interconnected state machines, the protocols between them, where there are actual cores running code (vs custom logic) etc.

09:19 <eddyb> ugh ignore me I think it's the caffeine talking

10:04 <electronic_eel> whitequark: poke

14:43 <kc8apf> eddyb: my boss tries to do that whenever he gets a new laptop. Basic architecture diagram is fairly simple. Cores inside specialized peripherals is a lot of guess work.

15:00 <eddyb> heh

15:48 <whitequark> electronic_eel: peek

15:48 <whitequark> electronic_eel: ah yeah layout

16:26 <davidc__> esden: any word on glasgow availability?

16:26 <davidc__> (just deciding whether I should order some PCBs today :) )

16:27 <esden> No and it still will be a while. iCEBreaker campaign has to be fulfilled first.

16:27 <davidc__> Fair enough. I'll fab my own boards1

16:27 <esden> :)

16:27 <davidc__> If anyone wants bare PCBs, ping me; I'll probably have a few extras to hand out

16:27 <tnt> Some people are courageous :p

16:30 <davidc__> Eh, its not that bad a board complexity wise. If there's sufficient interest, I could probably get a batch assembled; but my supply chain is fairly $$$, so the boards would probably be expensive assembled

16:33 <davidc__> (like, $200/ea expensive)

16:37 <miek> revb wasn't too bad, but for revc i'll probably wait for esden's :)

16:38 <electronic_eel> esden: did you see my photoshopped jig picture: https://imgur.com/XwYbHXf

16:38 <davidc__> miek: that was my plan too, but I'm itching to try the HW

17:29 <esden> electronic_eel: yeah it looks great :)

17:30 <electronic_eel> ok. whitequark wants to take a look at the layout and then I'm gonna order a few pcbs

17:45 <davidc__> electronic_eel: glasgow test PCB?

17:46 <electronic_eel> yeah, a pcb to mount into the test jig for production testing

17:47 <electronic_eel> see here: https://github.com/electroniceel/Glasgow/tree/test-jig/hardware/boards/test-jig

22:14 <furan-> howdy

22:15 <sorear> o/

22:16 <sorear> ok, but where’s pyrrole and thiophene

22:18 <furan-> lol

22:31 <electronic_eel> whitequark: if the layout review is a chore for you, then scratch it and I'm gonna order the pcbs at it is now

22:31 <electronic_eel> It's not that this is my first pcb layout

22:36 <tnt> electronic_eel: I can have a quick look if you want.

22:36 <electronic_eel> tnt: that would be nice

22:45 <tnt> That footprint for the solder bridge is ... terribe. triggers both DRC violations and reports unconnected, that's paiful.

22:46 <electronic_eel> I know. It is an older one I created with kicad 4.

22:46 <electronic_eel> I think the custom pads were just added recently

22:47 <electronic_eel> but I used it often on several of my boards. So I know this design works

22:52 <tnt> Other than that, it looks fine to me. There isn't really any critical parts (like high freq or high currents) anyway. Ground plane is mostly solid, usb traces are direct, power path is nice and wide ... so yeah, should work fine.

22:53 <electronic_eel> tnt: thanks

22:54 <tnt> np