<whitequark> heh, love the name
<niklas> do you have a strong opinion regarding the reset controller?
<niklas> would you hate me alot if I just replaced U7, U8 and U36 with two AMS1117? :D
* apo replaces niklas with three 555s
<whitequark> regarding U8 and U36: the specific part number is not critical, but please make sure that the LDO will be stable with the amount of ceramic capacitance we have. that was a factor in choosing the current LDOs and we had to reject a few
<whitequark> AMS1117 is also pretty huge even in SOT223 and I'm not sure if they'll fit?
<niklas> it would
<whitequark> hng on
<whitequark> you can't use AMS1117 for the 1.2V rail
<whitequark> first, they don't make the 1.2V variant
<whitequark> second, it has a minimum load current that under most conditions is larger than the FPGA core current
<whitequark> certainly during reset
<whitequark> the datasheet says AMS1117 requires a 22uF tantalum cap on the output
<whitequark> we only have ceramics
<niklas> this one has 1.2V
<whitequark> ah, AMS has an outdated datasheet
<whitequark> the other considerations still apply
<niklas> this one has 1.7mA minimum current
<niklas> but yeah SOT223 seems a bit overkill
<niklas> it's just very convinient that there are so many pin compatible variants
<whitequark> the core supply current for the FPGA is 1.140 mA
<whitequark> so you need to add a resistor to the output for stability
<tnt> I think the 1.2V version is really just the ADJ version ... since Vref=1.25v ...
<whitequark> the minimum core supply current*
<whitequark> just the static part
<niklas> well let's go for SOT-89
<niklas> tons of options for that as well
<whitequark> yes, that one is a lot better
<whitequark> but I'd still like electronic_eel to take another look in case I missed anything
<whitequark> now, regarding the reset generator
<whitequark> it actually serves two purposes. first, the FX2 datasheet says it does not have an internal reset circuit and requires an external reset generator
<whitequark> similarly, the FX2 doesn't have a brownout detector
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<whitequark> so after crowbaring an IO port, if the voltage does sag after all, the FX2 will glitch out
<whitequark> we actually did hit such a problem on revC0 because I screwed up the resistors for the reset generator
<whitequark> oh, also the FX2 has power sequencing requirements as well
<whitequark> er
<whitequark> the FPGA has
<niklas> okay but FPGA-reset is controlled by the FX
<niklas> so a simple single channel reset controller for the FX would be sufficient
<whitequark> don't forget FPGA power sequencing
<whitequark> actually, wait
<whitequark> iCE40UP5K has specific power sequencing requirements
<whitequark> but iCE40HX8K doesn't
<whitequark> that's kind of strange, but convenient for this. maybe daveshah knows why?
<whitequark> niklas: ok, so, the 3 channel reset generator is a holdover from revAB and AFAICT we can safely replace it with a 1 channel reset generator
<whitequark> good catch
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<whitequark> lol
<whitequark> which 1-ch reset generator are you going to use?
<niklas> MAX809J
<whitequark> are you sure you want to use a maxim chip
<whitequark> in my experience they tend to be expensive, unavailable, and sometimes unreliable. so far we avoided maxim parts entirely
<niklas> well JLC has >10000
<niklas> but I'm sure there is a pin-comptible alternative available
<whitequark> STM part second sourced by maxim seems fine
<niklas> and the MAX809 is also available von ON semicon :P
<whitequark> alright, that seems good then
<whitequark> which four capacitors are there on the back? PLL caps?
<niklas> jup
<niklas> what value is FB1?
<niklas> and I'm gonna use 10nF for those 12nF caps
<niklas> ahhhhh I haven't seen TPD3S014 yet
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<niklas> orrrr why does this project need to have so many exotic ICs D:
<niklas> what stackup?
<niklas> JLC7628 or JLC2313
<whitequark> unfortunately I don't recall how we picked FB1 and I never looked into power line filters
<awygle> i think we did a spice sim
<awygle> not sure tho
<awygle> or maybe it was recommended in the datasheet?
<whitequark> oh yeah
<whitequark> I think it was a sim since I don't see anything in the TPD3S014 datasheet
<whitequark> regarding ADC sampling caps: AFAICT that'll degrade its resolution, but we only use about 7 bits of it in the first place
<whitequark> wait, hm
<awygle> i have a sampling cap calculator i did for rev A
<awygle> if you haven't changed the ADC
<whitequark> we actually can just lower the sample rate
<whitequark> we can halve it one more time, to about 0.5 kHz
<whitequark> yes, it's on the schematic
<whitequark> er
<whitequark> I misread it, Csamp vs Fsamp
<whitequark> we can't halve Csamp
<whitequark> ok, so, we are actually only using 6 bits of resolution of the ADC (why did we use a 12 bit ADC for that?..)
<whitequark> since the UI actually just truncates after one decimal place and we don't guarantee anything beyond a 100 mV step
<whitequark> that means 10 nF Cext is just fine
<whitequark> can be as low as 2.5 nF
<whitequark> niklas: TPD3S014 is quite critical for overall board operation because it integrates a current limiter
<whitequark> TPD3S014, TPS73101, and LM3880 currently work together to ensure that shorting Vio to ground (or another power rail) is safe and ideally never causes the board to brown out, but if it does brown out, that the board will recover on its own
<whitequark> so any change to these parts requires repeating these tests
<whitequark> there's also a concern about damaging poorly designed motherboards with USB overcurrent conditions
<whitequark> this doesn't happen frequently but it does happen often enough that I'd like to see a tool which is inherently likely to overloa USB ports to try and prevent that
<whitequark> especially on revD which will have 5V exposed for the addons
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<niklas> there we go!
<niklas> it's missing some parts even through tey are available at jlc, because you can only select up to 10 different "extended components"
<whitequark> niklas: stackup: I don't think it matters for any of the signals on this board, and besides, we never required a particular stackup, so it would be too late now
<niklas> so I will have to check tomorrow if we can further simplify the design
<whitequark> doesn't C87 interfere with U36 etc?
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<niklas> yup, the rendering is too big
<niklas> should fit through
<whitequark> ah ok
<whitequark> that looks pretty good; I think so far I'm on board with all of the schematic changes you suggested, and they seem like a significant improvement in DFM
<whitequark> schematic/component rather
<whitequark> regaring further simplification, all that comes to mind is eliminating a few resistor values, but that won't help you with JLCSMT, will it?
<whitequark> ... also wait, is that $20@10 per board cost?
<niklas> jup
<niklas> see twitter :)
<JanHenrik> :D
<niklas> btw no, its 10$
<niklas> 200$ for 20 pcs ;)
<niklas> btw this is routing quality for now, might clean it up tomorrow
<niklas> it's late here already
<niklas> well there is this 0.68 Ohms resistor, 1Ohms and 2.2Ohms would be basic ;)
<whitequark> holy crap 10$ per board
<whitequark> you've beaten my *original* target for the simpler revA by 5 times
<niklas> ;)
<whitequark> that's incredibly impressive
<niklas> JLCST is incredible
<niklas> *JLCSMT
<whitequark> it'll be more than that in the end though, right? because of missing parts plus the ones soldered by end user
<niklas> yes
<niklas> roughtly 20$ missing
<whitequark> per board?
<niklas> 8,68$+6,91$+2x1,33$+2x1,25$
<niklas> per board, yes
<niklas> so 30$ for a fully assembled glasgow
<whitequark> plus manual work
<niklas> or, edinburgh for now
<niklas> yes, I think thats 10min work
<niklas> so ~5$
<whitequark> still very impressive
<whitequark> are the caps still all X5R ceramic?
<niklas> 4.7u is X5R
<niklas> 100n is X7R
<whitequark> right, the main thing is they aren't Y5V
<whitequark> that's quite excellent then
<whitequark> niklas: here's what I think: the DFM component changes (and things like the internal 3V3/1V2 LDOs) should definitely make it to upstream since they greatly benefit everyone
<whitequark> the changes to layout, power and protection circuits should be tested and if they work well, then they should ideally also get to upstream. but if for some reason they don't (don't currently see why but things happen), I would have no issue supporting Edinburgh as a functionally equivalent spin-off board and link it to everyone who wants a cheaper version
<whitequark> that said, if we can make it cheaper yet functionally equivalent then ideally everyone should be able to use that design.
<awygle> nice job niklas
<awygle> gonna have to go through those changes in detail
<awygle> i've been really into DF(Cheap) recently
<whitequark> awygle: can you open an issue tracking each of these changes as you do that?
<awygle> oof, responsibility
<awygle> yes, but not on any particular schedule, and only if nobody beats me to it. fair?
<whitequark> totally
<awygle> cool :D
* awygle bookmarks the relevant log page
<whitequark> depending on esden's schedule I suspect we might end up with revC2 that has DFM changes alone, and revC3 that goes all the way to one sided PCBA
<awygle> is esden the one that's been doing all the DFM on rev C? you've been cryptic about it on twitter :p
<esden> I was giving some suggestions...
<whitequark> it's a group effort
<esden> I do like the changes proposed by niklas though...
<awygle> i see
<awygle> i have been trying to learn about DFM and designing for cost and whatnot. although on my last board i apparently did that to such an extent that i completely fucked up an entire IC >_> oops
<whitequark> entire IC?
<whitequark> as in you killed it?
<awygle> you may have seen azonenberg posting about it on twitter, but i ... don't know what i was thinking. i didn't ground a thermal pad, shorted two regulators together, the decoupling is all wrong
<whitequark> ahh
<awygle> he's been trying to help me hack something into working well enough for me to test the design but at this point i may have to just respin :/ ah well that's what happens when you get sloppy
<whitequark> happens to all of us
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<_whitenotifier-3> [glasgow] jeremyherbert commented on issue #179: python modules not found after install - https://git.io/JvMOr
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<electronic_eel> janhenrik: niklas: nice work with the Edinburgh!
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<noopwafel> it is super cool to see; I spent a while trying to work out how it could be $30 but then I realized, connectors/headers/shipping/etc not included, I guess?
<noopwafel> but <$50 glasgow equivalent would be amazing
<electronic_eel> I saw the polymer cap is planned to be populated by JLC, I think that will make it hard to hand solder the fx2. I suggest to chose another extended part to be populated at jlcsmt instead
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<niklas> electronic_eel: my thoughts exactly
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<electronic_eel> niklas: do you want me to do a review of your component changes?
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<gruetzkopf> i might be interested in aquiring a board of this testrun ;) (i currently have a revB)
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<andres48> Hey there, I just finished my assembly of a revC1 board, and I'm trying to run the self test
<andres48> I'm getting this: ERROR: Parser error in line 619: syntax error
<tnt> Pastebin the complete error and command line please.
<andres48> Does anyone know if it is a python/environment/mainstream issue or it can be the board ?
<andres48> That's for "glasgow -vvv run uart -V 1.8"
<andres48> But same error on self test
<tnt> I suspect your fpga toolchain is too old ?
<tnt> It's not the board for sure ... it's still trying to build the fpga bitstream at that point.
<daveshah> Yeah, I'd say out of date Yosys
<tnt> that's the JSON parser right ?
<daveshah> Probably the ilang parser
<daveshah> nmigen uses some fairly recently added (0.9?) features
<andres48> I installed the stable package Yosys 0.9 from ArchLinux
<andres48> I passe this issue now, but I get another one
<andres48> I'll try the git version
<andres48> (I had the 0.8 before, so thank you for pointing in the good direction)
<andres48> :)
<daveshah> What issue do you get now?
<andres48> ERROR: Command syntax error: Unknown option or option in arguments.> synth_ice40 -abc9 -top top
<andres48> The "-abc9"
<daveshah> Yeah abc9 came after 0.9
<daveshah> git master should fix that
<tnt> Ouch ... why would glasgow use ABC9 ?!?
<tnt> Everytime I try it on ice40 the results are horrible.
<tnt> Works great on ECP5, but terribe on ice40 in my experience.
<daveshah> Hmm, back when I was at Symbiotic there was a small improvement on a few benchmarks so that sounds like a regression
<daveshah> If you get a chance it might be worth creating an issue with a test case where abc9 is noticeably worse on ice40
<electronic_eel> IIRC whitequark added the abc9 because of noticable speedup
<tnt> daveshah: Arf well, my benchmakrk is "ERROR: Assert `no_loops' failed in passes/techmap/abc9_ops.cc:288" with ABC9 ATM ...
<tnt> On 2 diffent designs even :/ Vex/picorv socs.
<andres48> Guys thank you for the advice, I'm kinda building the toolchain, so it'll take some time.
<andres48> It would be nice to note the upstream of the toolchains in the repo maybe ?
<awygle> ZirconiumX has been doing some more rigorous analysis of whether abc9 is worth it for various arches
<awygle> iirc the ice40 numbers were Not Great
<ZirconiumX> ...Christ awygle
<ZirconiumX> Could you have timed that any better?
<awygle> an awygle is never late, nor is he early
<ZirconiumX> There's also -flowmap, which is mostly there for experimentation, tnt
<ZirconiumX> I wouldn't use it in production, but it's not bad for a fully Yosys-internal flow
<tnt> ZirconiumX: my experience with flow map was that the size of the design exploded :p
<ZirconiumX> I mean, sure
<ZirconiumX> But compared to -noabc it's much better :P
<ZirconiumX> tnt: https://github.com/YosysHQ/yosys/issues/1792 <-- if you have anything you can donate to testing it would be nice.
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