04:00 <d1b2> <brainstorm> Hello folks, I have a very specific question... I have a working hand-assembled Glasgow Rev.C1 board. At the current nMigen development stage, how hard you reckon it'd take me to be able to read/write this TSOP56 Flash IC?: https://www.digikey.com/product-detail/en/cypress-semiconductor-corp/S29PL127J70TFI130/S29PL127J70TFI130-ND/5788094 I've noticed that nmigen-stdio's repo still does not have SPI support, so I guess the steps to get there would

04:00 <d1b2> be (veery high level point of view): 1) Implementing SPI support there. 2) Defining that flash Pinout and client-side read/write loops? Could any of you point me to alternative toolchains/example code, etc... if my outline would be too painful to implement at this stage of development? Thanks in advance!

04:13 <d1b2> <TiltMeSenpai> doesn't glasgow have spi support?

05:46 <d1b2> <tnt> @brainstorm That flash has more than 16 pins ...

07:00 <d1b2> <brainstorm> > @brainstorm That flash has more than 16 pins ... @tnt True, only 8 channels available on the Glasgow. How would one implement it? Fast shift registers and/or multiplexing?

07:12 <d1b2> <tnt> yeah you'd need external latching / muxing ...

08:31 <d1b2> <brainstorm> I wonder how FlashCat does it: https://www.embeddedcomputers.net/products/FlashcatUSB/

08:33 <noopwafel> does that flash IC support SPI?

08:35 <d1b2> <brainstorm> Yeah, an conforms with CFI: https://www.cypress.com/file/207091/download

08:36 <d1b2> <noopwafel> CFI just gives you some metadata for parallel interface flash

08:37 <d1b2> <h0m3us3r> i dont see that flash in the flashcat's supported list

08:38 <d1b2> <noopwafel> and I don't see any possibility for serial access in the datasheet of the flash chip you're looking at

08:39 <d1b2> <brainstorm> > i dont see that flash in the flashcat's supported list @h0m3us3r https://www.embeddedcomputers.net/products/FlashcatUSB_Mach1/

08:39 <d1b2> <noopwafel> ah, so I guess that has more pins 😄

08:40 <d1b2> <brainstorm> Indeed XD... ok, glasgow doesn't seem to match the specs I need, fair enough, thanks folks!

08:42 <d1b2> <noopwafel> shouldn't be a problem with some external muxing, but yeah sadly not straightforward

12:42 <whitequark> brainstorm: there is already support for parallel flashes

12:43 <whitequark> in fact you should be able to easily read and write that specific flash IC

12:43 <whitequark> do `glasgow run memory-prom --help` and follow the instructions

12:44 <whitequark> noopwafel: tnt: this is literally in the README... please don't misinform people

12:45 <_whitenotifier-b> [GlasgowEmbedded/glasgow] whitequark pushed 2 commits to master [+3/-0/±4] https://git.io/JJPDM

12:45 <_whitenotifier-b> [GlasgowEmbedded/glasgow] whitequark 5a9f4f4 - applet.program.avr.jtag: new applet. (WIP)

12:45 <_whitenotifier-b> [GlasgowEmbedded/glasgow] whitequark 37ad79a - README: parallel memories can be written too, not just read.

12:45 <whitequark> argh

12:46 <_whitenotifier-b> [GlasgowEmbedded/glasgow] whitequark pushed 1 commit to master [+0/-0/±1] https://git.io/JJPD9

12:46 <_whitenotifier-b> [GlasgowEmbedded/glasgow] whitequark a450d1e - README: parallel memories can be written too, not just read.

12:46 <_whitenotifier-b> [glasgow] Error. The Travis CI build could not complete due to an error - https://travis-ci.org/github/GlasgowEmbedded/glasgow/builds/715825611?utm_source=github_status&utm_medium=notification

12:56 <_whitenotifier-b> [glasgow] Success. The Travis CI build passed - https://travis-ci.org/github/GlasgowEmbedded/glasgow/builds/715825747?utm_source=github_status&utm_medium=notification

13:02 <d1b2> <noopwafel> Oh nice, I thought you would need the shift ICs

13:03 <tnt> But ... you _do_ need external circuitry ... unless I'm missing something.

13:03 <whitequark> you do need it

13:03 <whitequark> the difference is that it's actually well supported

13:03 <whitequark> you won't need to fiddle with shift registers *and* then fiddle with gateware

13:03 <d1b2> <noopwafel> Sorry, anyway

13:03 <whitequark> you can just add some shift registers and then everything else will work right away

13:03 <tnt> You also need to dump it twice just because ... 16 bits databus ..

13:05 <whitequark> tnt: huh, my bad, sorry

13:05 <tnt> Not sure how that works for write actually, is there a byte mask ?

13:05 <whitequark> i thought it has ~BYTE

13:05 <whitequark> but... it doesn't

13:05 <whitequark> yes, then it's just not possible to write, you are right

13:05 <d1b2> <noopwafel> Easy to do it twice anyway

13:05 <d1b2> <noopwafel> For read

13:08 <whitequark> gah, should not use IRC while not fully awake :/